HDMI Link Output Interface - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)
Document ID
PG235
Release Date
2023-10-18
Version
3.2 English

The following table shows the HDMI Link interface signals. This interface runs at the link_clk clock rate.

Table 1. HDMI Link Interface
Name I/O Width Description
link_clk I 1 Link clock
LINK_DATA0_OUT_tdata 1 O 40 Link data 0
LINK_DATA0_OUT_tvalid O 1 Link Data 0 Valid
LINK_DATA1_OUT_tdata 1 O 40 Link data 1
LINK_DATA1_OUT_tvalid O 1 Link Data 1 Valid
LINK_DATA2_OUT_tdata 1 O 40 Link data 2
LINK_DATA2_OUT_tvalid O 1 Link Data 2 Valid
  1. The width of the LINK_DATA out signals is 40 bits always, but the valid data is present only on the LSB ppc*10 bits ([(ppc*10)-1:0]). The MSBs are appended with 0s in 2PPC mode.