Hardware - 3.2 English

The example design is built around the HDMI 1.4/2.0 Transmitter Subsystem (HDMI_TX_SS), the HDMI 1.4/2.0 Receiver Subsystem (HDMI_RX_SS) (Optional), and the Video PHY Controller (VPHY) /HDMI GT Subsystem core and leverages existing AMD IP cores to form the complete system. The following two figures are illustrations of the overall HDMI example design block diagram targeting various AMD evaluation kits.

Figure 1. KC705/KCU105/ZC706/VCU118 HDMI Example Design Block Diagram

Figure 2. ZCU102/ZCU104/ZCU106/VCK190/VMK180 HDMI Example Design Block Diagram

Important: When an unpowered HDMI source is connected to the HDMI receiver in a pass-through system, the HDMI example design UART can get flooded with a Starting Colorbar message because of a limitation of the ZCU102 board design.

The Video PHY Controller /HDMI GT Subsystem core has been configured for the HDMI application that allows transmission and reception (optional) of HDMI video/audio to and from the HDMI 2.0 mezzanine card or on-board HDMI 2.0 circuitry.

Figure 3. KC705/KCU105/ZC706/VCU118 HDMI Reference Design Clock and Datapath Diagram

Figure 4. ZCU102/ZCU104/ZCU106/VCK190/VMK180 HDMI Reference Design Clock and Datapath Diagram

Note: The ZCU104 Evaluation Kit has IDT8T49N241 as the clock generator.

Important: The TI HDMI cable driver chip DP159 is used in all the example design, either on the evaluation board itself or on the inrevium TB-FMCH-HDMI4K FMC mezzanine card. In the HDMI example design software, a sample DP159 driver is provided as reference. In HDMI example design, DP159 mode depends on HDMI line rate. Automatic re-driver to re-timer crossover at 1.0 Gbps (default) for HDIM1.4, Automatic re-timer for HDMI2.0 The settings have not been calibrated for various use cases. If you are using the DP159 in your product, you need to adjust the settings based on the circuit design. Some further fine tuning might still be needed depending on the compliance results.

TMDS DATA PCB trace rules required to meet HDMI compliance requirements for the TMDS181 (only when RX is used) and SN68DP159 devices are as follows.

Inter-pair skew for DATA[0:2] lanes must be:

Max 10 ps inter-pair skew FPGA→ retimer
Max 10 ps inter-pair skew retimer→ connector

Intra-pair skew for DATA[0:2] lanes must be:

Max 1 ps intra-pair skew FPGA→ retimer
Max 1 ps intra-pair skew retimer→ connector
Target impedance to be 100Ω ±7% (Max ±10%)
- A single excursion is permitted out to a max/min of 100Ω ±25% and of a duration less than 250 ps

In pass-through mode, the Video PHY Controller /HDMI GT Subsystem core receives the high-speed serial video stream, converts it to parallel data streams, forwards it to the HDMI_RX_SS core, which extracts the video and audio streams from the HDMI stream and converts it to separate AXI video and audio streams. The AXI video goes through the TPG core and the AXI audio goes through a customized audio generation block. The two AXI streams eventually reach the HDMI_TX_SS core, which converts the AXI video and audio streams back to an HDMI stream before being transmitted by the Video PHY Controller /HDMI GT Subsystem core as a high-speed serial data stream. The transition minimized differential signaling (TMDS) clock from the HDMI In interface is forwarded to the HDMI TX transceiver through the SI53xx clock generator in the HDMI 2.0 FMC card or on-board HDMI 2.0 circuitry.

Note: The ZCU104 uses a different clock generator, the IDT 8T49N24x. A sample driver is provided as part of example application software. It is not calibrated for the best performance to pass compliance. You might need to fine tune its settings in your design if you are using the same chip.

In TX-only mode, the colorbar pattern is generated by the TPG as an AXI video stream and the low frequency audio is generated by the customized audio processing block as an AXI audio stream. The two streams are forwarded to the HDMI_TX_SS for HDMI stream conversion and then to the Video PHY Controller /HDMI GT Subsystem for transmission.

High-level control of the system is provided by a simplified embedded processor subsystem containing I/O peripherals and processor support IP. A clock generator block and a processor system reset block supply clock and reset signals for the system, respectively. See the following two figures for block diagrams of the three types of processor subsystems supported by the HDMI example design flow.

Figure 5. HDMI Reference Design Block Diagram (MicroBlaze)

Figure 6. HDMI Reference Design Block Diagram (Zynq or Zynq UltraScale+ MPSoC or Versal Adaptive SoC)