Because the HDMI 1.4/2.0 TX Subsystem is hierarchically packaged, you can configure it by setting the parameters in the AMD Vivado™ Integrated Design Environment (IDE) interface and the subsystem creates the required hardware accordingly.
A high-level block diagram of the HDMI 1.4/2.0 TX Subsystem is shown in the following figure.
The HDMI 1.4/2.0 TX Subsystem is constructed on top of an HDMI TX core. Various supporting modules are added around the HDMI TX core with respect to your configuration. The HDMI TX core is designed to support native video interface, however many of the existing video processing IP cores are AXI4-Stream-based. It is a natural choice to add supporting modules (Video Timing Controller and AXI4-Stream to Video Out Bridge) to allow the HDMI 1.4/2.0 TX Subsystem to support AXI4-Stream-based video input. Doing this allows the HDMI 1.4/2.0 TX Subsystem to work seamlessly with other AMD video processing IP cores. The HDMI 1.4/2.0 TX Subsystem has a built-in capability to optionally support both HDCP 1.4 and HDCP 2.3 encryption.
The HDMI 1.4/2.0 TX Subsystem supports the following types of video interface:
- AXI4-Stream Video Interface
- Native Video Interface
- Native Video (Vectored Data Enable (DE)) Interface
The following figure shows the internal structure of the HDMI 1.4/2.0 TX Subsystem when AXI4-Stream is selected as the video interface. In this illustration, both HDCP 1.4 and HDCP 2.3 are selected and both Video over AXIS compliant NTSC/PAL Support and Video over AXIS compliant YUV420 Support are selected.
The HDMI 1.4/2.0 TX Subsystem also provides an option to support a native video interface. Some applications require support of customized resolutions, which are not divisible by the PPC setting (4 or 2). Therefore, the HDMI 1.4/2.0 TX Subsystem also provides a native video (Vectored DE) interface option to enable this application. When native video interface (with or without Vectored DE) is selected, the HDMI 1.4/2.0 TX Subsystem is constructed without the Video Timing Controller and AXI4-Stream to Video Out bridge. Therefore, the HDMI 1.4/2.0 TX Subsystem is allowed to take native video from its own video devices and convert into HDMI signals. In native video mode, the HDMI 1.4/2.0 TX Subsystem still has a built-in capability to optionally support both HDCP 1.4 and HDCP 2.3 encryption.
The following figure shows the internal structure of the HDMI 1.4/2.0 TX Subsystem when native video is selected as the video interface. In this illustration, both HDCP 1.4 and HDCP 2.3 are selected.
The following figure shows the internal structure of the HDMI 1.4/2.0 TX Subsystem when Native Video (Vectored DE) interface is selected as the video interface. In this illustration, both HDCP 1.4 and HDCP 2.3 are selected.
The data width of the video interface is configured in the Vivado IDE by setting the Number of Pixels Per Clock on Video Interface and the Max Bits Per Component parameters.
The audio interface is a 32-bit AXI4-Stream slave bus, which transports multiple channels of uncompressed audio data to the subsystem.
The CPU interface is an AXI4-Lite bus interface, which is connected to a MicroBlaze™ ™, Zynq 7000 SoC, or AMD Zynq™ UltraScale+™ MPSoC processor. Multiple sub-modules are used to construct the HDMI 1.4/2.0 TX Subsystem and all the sub-modules which require software access are connected through an AXI crossbar. Therefore, the MicroBlaze, AMD Zynq™ 7000 SoC, or AMD Zynq™ UltraScale+™ MPSoC processor is able to access and control each individual sub-modules inside the HDMI 1.4/2.0 TX Subsystem.
The CPU interface is an AXI4-Lite bus interface, which is connected to a MicroBlaze™ ™, Zynq 7000 SoC, AMD Zynq™ UltraScale+™ MPSoC, or AMD Versal™ adaptive SoC processor. Multiple sub-modules are used to construct the HDMI 1.4/2.0 TX Subsystem and all the sub-modules which require software access are connected through an AXI crossbar. Therefore, the MicroBlaze, Zynq 7000 SoC, Zynq UltraScale+ MPSoC, or Versal adaptive SoC processor is able to access and control each individual sub-modules inside the HDMI 1.4/2.0 TX Subsystem.
The HDMI 1.4/2.0 TX Subsystem device driver has an abstract layer of API to allow you to implement certain functions. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers).
The subsystem converts the video stream and audio stream into an HDMI stream, based on the selected video format set by the processor core through the CPU interface. The subsystem transmits the HDMI stream to the PHY Layer (Video PHY Controller) which converts the data into electronic signals which are sent to an HDMI sink through an HDMI cable.
The subsystem converts the video stream and audio stream into an HDMI stream, based on the selected video format set by the processor core through the CPU interface. The subsystem transmits the HDMI stream to the PHY Layer (Video PHY Controller/HDMI GT Subsystem) which converts the data into electronic signals which are sent to an HDMI sink through an HDMI cable.
The subsystem also supports the features described in the following sections.