Native Video Interface - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)
Document ID
PG235
Release Date
2023-10-18
Version
3.2 English

The following table shows the signals for the native video interface. This interface is a standard video interface and runs at the video_clk clock rate. The data width is user-configurable in the Vivado IDE by setting Max Bits Per Component (BPC) and Number of Pixels Per Clock on Video Interface (PPC).

Table 1. Native Video Interface
Name I/O Width Description
video_clk 1 I 1 Video clock
NATIVE_VID_IN_active_video 5 I 1 Active video
NATIVE_VID_IN_data I video_data_width 3 Data
NATIVE_VID_IN_hsync 5 I 1 Horizontal sync
NATIVE_VID_IN_vsync 5 I 1 Vertical sync
  1. video_clk is generated by the Video PHY Controller .
  2. When native video/native video (Vectored DE) interface is selected, s_axis_video_aclk and s_axis_video_aresetn are removed from the HDMI 1.4/2.0 TX Subsystem interface ports.
  3. video_data_width = 3*BPC*PPC.
  4. When native video interface is selected, there is no hardware reset.
  5. You must provide the correct video timing information. You can choose to use the AMD Video Timing Controller (vtc) or design your own vtc module to generate the timing control signals for the native video interface.