Running the Example Design - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

Document ID
PG235
Release Date
2023-10-18
Version
3.2 English
  1. Open the Vivado Design Suite and create a new project.
  2. In the pop-up window, press Next until you get to the page to select the AMD part or board for the project.

    Note: Ensure that you have selected the Versal board in the project setup in the Vivado Design Suite. To do this, when you get to the Default Part screen, select the Boards tab, and select Install/Update Boards. This takes you to the Xhub Stores, where you can right-click on the VCK190/VMK180 board and select Install to install the VCK190/VMK180 board support files.
  3. Select the target board, then click Next > Finish. (KC705, KCU105, ZC706, ZCU102, ZCU104, ZCU106, VCU118, VCK190, and VMK180 are supported.)
  4. A Vivado Project opens. In Flow Navigator, PROJECT MANAGER, click IP Catalog to open it. Then double-click HDMI 1.4/2.0 Transmitter Subsystem in Video Connectivity.

  5. A Customize IP window opens. Configure the HDMI 1.4/2.0 TX Subsystem, then select OK.
    1. Refer to the Design Flow Steps chapter for a detailed description on Customizing and Generating the Subsystem.
    2. You can rename the IP component name, which is used as example design project name.
    3. The native video interface, including the native video (Vectored DE) interface, is not supported in the example design flow.




  6. The Generate Output Products dialog box opens. Select Generate.
    Note: You can optionally select Skip if you only want to create an example design and leave the IP generation to a later stage.


  7. The IP component with provided name is added to Design Sources. Right-click on it and select Open IP Example Design.

  8. Choose the target Example project directory, then select OK.
  9. A new Vivado project launches, in which an HDMI Example Design is generated with Block Design to show the system structure. Select Run Synthesis, Implementation, and Generate Bitstream to build the design. An overall system IP integrator block diagram of the KC705-based example design is shown:

Note: If you close the block design and re-open it again, then re-run Validate Design, the following warning message, which does not have any functionality impact, is shown in the console.
WARNING: [BD 41-1731] Type mismatch between connected pins: /v_hdmi_tx/
s_axis_video_aresetn_out(undef) and /v_axi4s_vid_out/aresetn(rst)