The Example Design tab is shown in the following figure.
Figure 1. Example Design Tab (HDCP Not Included)
- Design Topology
-
Allows you to
choose the topology of example design to be generated. The allowable options
are Pass-Through and RX Only.
- Pass-Through showcases the HDMI system built with one HDMI TX Subsystem and one HDMI RX Subsystem, sharing the same Video PHY Controller/HDMI GT Subsystem.
- RX-Only showcases the HDMI
system built with only one HDMI RX Subsystem and Video PHY Controller
. A Frame CRC helper core is added to the RX-Only
topology to facilitate system monitor and debugging.Figure 2. RX-Only Topology with Frame CRC Help Core
- Axilite Frequency
- Allows you to choose the AXI4-Lite CPU clock. In this release, the following options have
been verified.
- 7 series
- 50 MHz, 100 MHz, 150 MHz
- UltraScale/UltraScale+ Devices
- 50 MHz, 100 MHz, 150 MHz, 200 MHz
- Versal Adaptive SoCs
- 100 MHz
- Video Phy Controller Setting
- Allows the configuration of the Transmitter PLL type and Receiver PLL Type to the Video PHY Controller /HDMI GT Subsystem prior generating the example design. It also allows user to selectively opt-out the NI-DRU to optimize resource use if the video resolution they plan to support does not require NI-DRU. See the Video PHY Controller LogiCORE IP Product Guide (PG230) or the HDMI GT Controller LogiCORE IP Product Guide (PG334) for details about NI-DRU requirements for Versal adaptive SoCs.
- Example Design Overview
- A system block diagram to show the overview of the example design to be generated.
Important: When the example design targets the VCU118 board and Design Topology is
set to Pass-Through, the Include NIDRU option under the Video PHY Controller setting is grayed out and unchecked by default.
Note: When the AXI4-Lite clock is set at a higher
frequency, it is more likely to have timing violations. You must adjust the clock rate
to achieve timing closure without impacting system performance.