HDMI Link Input Interface - 3.2 English

HDMI 1.4/2.0 Receiver Subsystem v3.2 Product Guide (PG236)

Document ID
PG236
Release Date
2023-10-18
Version
3.2 English

The following table shows the HDMI Link interface signals. This interface runs at the link_clk clock rate.

Table 1. HDMI Link Interface
Name I/O Width Description
link_clk I 1 Link clock
LINK_DATA0_IN_tdata 1 I 40 Link data 0
LINK_DATA0_IN_tvalid I 1 Link Data 0 Valid
LINK_DATA1_IN_tdata 1 I 40 Link data 1
LINK_DATA1_IN_tvalid I 1 Link Data 1 Valid
LINK_DATA2_IN_tdata 1 I 40 Link data 2
LINK_DATA2_IN_tvalid I 1 Link Data 2 Valid
  1. The width of LINK_DATA inputs is always 40 bits. Out of which, only [(ppc*10)-1 :0] bits are used by the IP. The MSBs are ignored in 2PPC mode.