Status and Control Data Channel (SCDC) - 3.2 English

The subsystem supports the SCDC Registers for HDMI 2.0 TMDS configuration as defined in Table 10-19 of the HDMI 2.0 specification.

The following APIs are available in the driver to use this feature.

• XV_HdmiRx_DdcScdcEnable is used to enable the SCDC
• XV_HdmiRx_DdcScdcClear is used to clear the SCDC
• XV_HdmiRxSs_Write_ScdcRegister is used to write data into SCDC Registers
  Note: SCDC register 0x01,0x02,0x10,0x20,0x21, and 0x40 are handled by H/W directly. These registers should not be written by using above API.