- Any time during the core operation, the core can be disabled using the core_config register.
- After the core is disabled, wait/poll until the control ready bit is set in the core_config register.
- Then you can re-enable the core after programming new settings.
Note: Any changes to bllp_mode and blanking packet type
values during core operation take effect during the next BLLP period.
Figure 1. Core Programming Sequence - 2
