Required Constraints
This section is not applicable for this IP subsystem.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP subsystem.
Clock Frequencies
See Clocking.
Clock Management
The MIPI DSI TX Subsystem sub-core MIPI D-PHY uses an MMCM to generate the general interconnect clocks, and the PLL is used to generate the serial clock and parallel clocks for the PHY. The input to the MMCM is constrained as shown in MIPI D-PHY LogiCORE IP Product Guide (PG202). No additional constraints are required for the clock management.
Clock Placement
This section is not applicable for this IP subsystem.
Banking
The MIPI DSI TX Subsystem provides the Pin Assignment Tab option to select the HP I/O bank. Clock lane and data lane(s) are implemented on the selected I/O bank BITSLICE(s).
Transceiver Placement
This section is not applicable for this IP subsystem.
I/O Standard and Placement
The MIPI standard serial I/O ports should use MIPI_DPHY_DCI for the I/O standard in the XDC file for UltraScale+ family. The LOC and I/O standards must be specified in the XDC file for all input and output ports of the design. The MIPI DSI TX Subsystem MIPI D-PHY sub-core generates the I/O pin LOC for the pins that are selected during IP customization for UltraScale+ designs. No I/O pin LOC are provided for 7 series MIPI D-PHY IP designs. You have to manually select the clock capable I/O for 7 series TX clock lane and restrict the I/O selection within the I/O bank for MIPI D-PHY TX.
It is recommended to select the I/O bank with VRP pin connected for UltraScale+ MIPI D-PHY TX IP core. If the VRP pin is present in another I/O bank in the same I/O column of the device the following DCI_CASCADE XDC constraint should be used. For example, I/O bank 65 has a VPR pin and the D-PHY TX IP is using the I/O bank 66.
set_property DCI_CASCADE {66} [get_iobanks 65]