# D-PHY LP HS offset - 2.3 English

## MIPI DSI Transmitter Subsystem Product Guide (PG238)

Document ID
PG238
Release Date
2022-10-19
Version
2.3 English

The core does not consider the LP to HS delay in the video timing calculations by default. Hence, the user sees slightly less Frames Per Second (FPS) than intended. In situations where the user needs to consider the D-PHY LP to HS latency, the user is required to program the register given below.

The D-PHY LP to HS (more specifically the time from PPI signal txrequesths to txreadyhs) delay varies based on Line Rate (Mb/s), LPX Period (ns), internal design logic, and CDC stages.

User Inputs:

P1 = UI in ns

P2 = LPX Period in ns

P3 = INT(PPI Byteclk in ns) is calculation to converts the specified value into an integer number.

P4 = PPI Byteclk in ns (with decimal places)

Table 2-19:      Internal parameters L1

Linerate

L1

<150

INT(P1)

150 to <300

INT(P1*2)

301 to <600

INT(P1*4)

601 and above

P3

L2 = P2 + 25

L3 = 85 + 6*P1

L4 = ((L3-3*L1)/5)-1

L5 = (L4*5 + L2)/P4

L6 = INT((105+6*P1)/P3) + 4

LP-HS delay = L5 + L6

Example LP-HS delay for certain line rates are given below:

Table 2-20:      Example LP-HS delay for certain line rates

Line rate

P1

P2

P3

L1

P4

L2

L3

L4

L5

L6

LP-HS Delay

80

12.5

50

100

12

100

75

160

23

1

5

6

150

6.666667

50

53

13

53.33333333

75

125

16

2

6

8

550

1.818182

50

14

7

14.54545455

75

95.90909091

13

9

12

21

1000

1

50

8

8

8

75

91

12

16

17

33

1188

0.841751

50

6

6

6.734006734

75

90.05050505

13

20

22

42

1440

0.694444

50

5

5

5.555555556

75

89.16666667

13

25

25

50

Due to CDC stages and decimal numbers of byteclk period, the user may need to program a slightly higher or lower value obtained in the above table to get the closer FPS on the hardware.

The final value to program is “LP-HS Delay” * DSI Lanes.

Table 2-21:      Video Timing (D-PHY LP HS offset) (0x68)

Bits

Name

Reset Value

Access

Description

31:16

Reserved

NA

NA

Reserved

15:0

D-PHY LP HS offset

0x0

R/W

To offset D-PHY LP to HS transition delay in the video timing calculations

Table 2-22:      Timing Register-5 (0x6C)

Bits

Name

Reset Value

Access

Description

31:8

Reserved

NA

NA

Reserved

7:0

VFP

0x0

R/W

MSB 8bits of the 16bit Vertical front porch lines count