Example Configuration 3 - 2.3 English

Consider an exemplary MIPI DSI Panel with the following specifications:

Note:   For compressed data type, you are expected to pump in the compressed data. Core passes through those stream of data without any conversion. In the current example, it is expected that the 640 pixels of input stream is compressed to 500 pixels.

To generate the values and set timing registers based on the above example configuration, perform the following:

HACT(WC) = Active pixels per line * Bits per pixel/8

= 500*8/8

= 500 (decimal) -> 0x1F4

BLLP(WC) = BLLP Pixels per line * Bits per pixel/8

                 = 140*8/8

                = 140(decimal) -> 0x8C

   VACT = Active lines per frame

            = 480(decimal) -> 0x1E0

1.Get total line-time in pixel clock.

Pixel Frequency = 50Mhz

Pixel clock period = 1000/50 = 20ns

Total pixel in one line = 500+140+100 = 740

Total line time = 740*20 = 14800 ns

2.Calculate blanking time.

Byte clock(PPI) frequency = Line-rate/8 = 500/8 = 62.5Mhz

Byte clock period = 1000/62.5 = 16 ns

HACT Duration = Pixels* (Bytes per pixel) * Byte clk Period/ Lanes

= (500 * 1 * 16) /2

= 4000 ns

BLLP Duration = Pixels* (Bytes per pixel) * Byte clk Period/ Lanes

= (140 * 1 * 16) /2

= 1120 ns

Blanking time(BLLP+Horizontal Blanking) = Line-time - HACT Duration - BLLP Duration

= 14800 - 4000 -1120

= 9680 ns

WC(Bytes) to meet "Blanking time" of 9680 ns

= Blanking time * Lanes / (Byte Period)

= 9680 * 2 / 16

= 1210

3.Get timing parameter based on Video mode

Video mode: Burst Mode

One line is composed of HSS + HBP + HACT + BLLP + HFP

Horizontal Sync Start (HSS) -> Short packet ->4 bytes

HBP/HACT/BLLP/HFP -> Long packet -> 4 bytes header + Payload + 2 bytes CRC

Total of 4 + 4*6 = 28 bytes are covered in header and footer.

Available blanking WC = 1210- 28 = 1182

4.Divide the total available WC across available blanking parameters HBP and HFP. Considering a ratio of 1:2 gives: (The values for HBP and HFP are the distribution of the horizontal blanking words across these parameters. In the examples, Xilinx tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays may have specific requirements. Hence, please consult the data sheet for your display.)

Horizontal Back Porch (HBP) = 394

Horizontal Front Porch (HFP) = 1182 - 394

= 788

5.Set applicable horizontal timing registers with above calculated values.

HBP = 394(decimal) -> 0x18A

HFP = 788(decimal) -> 0x314

6.Divide the total available vertical blanking lines between VSA, VBP, and VFP. Considering a ratio of 1:1:1 gives: (The values for HBP and HFP are the distribution of the horizontal blanking words across these parameters. In the examples, Xilinx tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays may have specific requirements. Hence, please consult the data sheet for your display.)

VSA =  5 (decimal) -> 0x05

VBP =  5 (decimal) -> 0x05

VFP = 5 (decimal) -> 0x05

7.Final consolidate set of horizontal and vertical timing parameters for a DSI panel with 640x480@60 fps, 2-Lane, 500 Mb/s, Compressed data type, Video clock of 50 MHz are as specified below:

HACT = 0x1F4

BLLP(0x50[15:0] = 0x8C

HBP = 0x18A

HFP = 0x314

 

VACT= 0x1E0

VSA = 0x05

VBP = 0x05

VFP = 0x05