•1-4 Lane Support
•Line rates ranging from:
°260 to 2500 Mb/s for Versal® ACAPs
°80 to 2500 Mb/s, refer to the data sheet of your device
•Supports different data types with fixed Virtual Channel Identifier (VC) of 0. For list of data types refer to "DSI Data type" GUI parameter
•Programmable EoTp generation support
•ECC generation for packet header
•CRC generation for data bytes (optional)
•Optional DCS Command mode support to send command packets long/short
•Pixel-to-byte conversion based on data format
•AXI4-Lite interface to access core registers
•Compliant with AXI4-Stream Video IP and System Design Guide (UG934) [Ref 3] for input video stream
•Interrupt generation to indicate subsystem status information
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IP Facts Table |
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Subsystem Specifics |
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Supported Device Family(1) |
Versal® ACAP, UltraScale+™, Zynq® UltraScale+ MPSoC, Zynq®-7000 SoC, 7 series FPGAs |
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Supported User Interfaces |
AXI4-Lite, AXI4-Stream |
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Resources |
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Provided with Subsystem |
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Design Files |
Encrypted RTL |
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Example Design |
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Test Bench |
Not Provided |
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Constraints File |
XDC |
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Simulation Model |
Not Provided |
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Supported |
Standalone and Linux |
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Tested Design Flows(3) |
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Design Entry |
Vivado® Design Suite |
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Simulation |
For supported simulators, see the |
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 66769 |
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All Vivado IP Changes Logs |
Master Vivado IP Changes Logs: 72775 |
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Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). 3.For the supported versions of the tools, see the 4.MIPI CSI-2 Receiver Subsystem Product Guide (PG232) [Ref 5] uses this IP in example design. |
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