Global Interrupt Enable Register - 2.3 English

MIPI DSI Transmitter Subsystem Product Guide (PG238)

Document ID
PG238
Release Date
2022-10-19
Version
2.3 English
Table 2-6:      Global Interrupt Enable register (0x20)

Bits

Name

Reset Value

Access

Description

31:1

Reserved

NA

NA

Reserved

0

Global Interrupt enable

0x0

R/W

Master enable for the device interrupt output to the system

1: Enabled: Corresponding IER bits are used to generate interrupt.

0: Disabled: Interrupt generation blocked irrespective of IER bits.