The MIPI DSI TX Subsystem GUI do not have I/O Assignment tab for Versal® ACAPs. Instead you need to use consolidated I/O planning in the main Vivado IDE Planning that is nibble planner. You can select any I/O for the clock and data lanes for the selected XPIO bank.
Detailed steps on how to perform the Vivado IDE planning is detailed under section "I/O Planning for Versal Advanced IO Wizard” in Advanced I/O Wizard LogiCORE IP Product Guide (PG320) [Ref 18]. While selecting IOs in a bank across nibbles, you need to ensure the Inter-nibble, Inter-byte clock guidelines are followed. Refer to the "Clocking" section in Versal ACAP SelectIO Resources Architecture Manual (AM010) [Ref 19].