Implementing More Than 4-Lane DSI-TX Design - 2.3 English

MIPI DSI Transmitter Subsystem Product Guide (PG238)

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2.3 English

The existing MIPI DSI TX Subsystem allows a maximum of 4 lanes. Guidelines to achieve DSI designs with higher lane requirements (for example, an eight lane design) are listed below:

1.After the stream source, you need a splitter module which splits the incoming video stream into two streams; the left-half and the right-half image.

2.Each splitter output then feeds to one DSI 4 lanes instance.

3.The DSI 8-lane Receiver should be following reverse to combine the images.

4.You need to program each DSI-TX 4 lanes instance timing parameters based on half image rather than full image timing parameters.

5.In DSI-RX, one DSI instance reconstructs left half of the image and the other DSI instance reconstructs the right half of the image.

The 8-lane implementation using two 4-lane MIPI DSI TX instances is shown in This Figure.

Figure 3-1:      Eight-Lane DSI Implementation

X-Ref Target - Figure 3-1