Resets - 2.3 English

MIPI DSI Transmitter Subsystem Product Guide (PG238)

Document ID
Release Date
2.3 English

DSI Transmitter Controller has one hard reset (s_axis_aresetn) and one register based reset (soft reset).

s_axis_aresetn: All the core logic blocks reset to power-on conditions including registers.

The soft reset resets the Interrupt Status register (ISR) of DSI TX Controller and does not affect the core processing.

The subsystem has one external reset port:

s_axis_aresetn: Active-Low reset for the subsystem blocks

The duration of s_axis_aresetn should be a minimum of 40 dphy_clk_200M cycles to propagate the reset throughout the system.

The reset sequence is shown in This Figure.

Figure 3-5:      Reset Sequence

X-Ref Target - Figure 3-5


Table: Subsystem Components summarizes all resets available to the MIPI DSI TX Subsystem and the components affected by them.

Table 3-6:      Subsystem Components



MIPI DSI TX Controller

Connected to s_axi_aresetn core port


Inverted signal connected to core_rst port

AXI Crossbar

Connected to aresetn port

Note:   The effect of each reset (s_axis_aresetn) is determined by the ports of the sub-cores to which they are connected. See the individual sub-core product guides for the effect of each reset signal.