DSI Transmitter Controller has one hard reset (s_axis_aresetn) and one register based reset (soft reset).
•s_axis_aresetn: All the core logic blocks reset to power-on conditions including registers.
•The soft reset resets the Interrupt Status register (ISR) of DSI TX Controller and does not affect the core processing.
The subsystem has one external reset port:
•s_axis_aresetn: Active-Low reset for the subsystem blocks
The duration of s_axis_aresetn should be a minimum of 40 dphy_clk_200M cycles to propagate the reset throughout the system.
The reset sequence is shown in This Figure.
Table: Subsystem Components summarizes all resets available to the MIPI DSI TX Subsystem and the components affected by them.
Note: The effect of each reset (s_axis_aresetn) is determined by the ports of the sub-cores to which they are connected. See the individual sub-core product guides for the effect of each reset signal.