Clock and Rest Signals Interface Ports - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)
Document ID
PG239
Release Date
2022-06-03
Version
1.0 English
Table 1. Clock and Reset Signals
Port Name Width I/O Clock Description
phy_refclk 1 Input refclk Reference clock for fabric logic. This clock must be driven directly from a BUFG_GT. The recommended reference clock is 100 MHz. This clock is expected to be free running and stable. This reference clock can be either synchronous or asynchronous. In synchronous mode, the PPM is 0. In asynchronous mode, the PPM is up to ±300 or 600 PPM worst case.
  • 100 MHz (default)
  • 125 MHz
  • 250 MHz
phy_gtrefclk 1 Input refclk Reference clock for GT. This clock must be driven directly from an IBUFDS_GTE3/IBUFDS_GTE4. Same definition and frequency as phy_refclk.
phy_rst_n 1 Input Asynchronous When logic Low, this signal resets the PHY. This must be connected to PCIe PERST_N. Polarity is Active Low.
pipe_coreclk 1 Output coreclk Core clock options:
  • 250 MHz
  • 500 MHz
pipe_userclk 1 Output userclk User clock options:
  • 62.5 MHz
  • 125 MHz
  • 250 MHz
  • 500 MHz

pipe_userclk is edge-aligned and phase-aligned to pipe_coreclk.

pipe_mcapclk 1 Output mcapclk Additional clock options:
  • 62.5 MHz
  • 125 MHz (default)

pipe_mcapclk is edge-aligned and phase-aligned to pipe_coreclk.
phy_pclk 1 Output pclk PIPE interface clock options:
  • 125 MHz: Gen1 operating speed
  • 250 MHz: Gen2, Gen3, Gen4 operating speed

phy_pclk is edge-aligned, but not phase-aligned to pipe_coreclk and pipe_userclk.