|Port Name||Width||I/O||Clock Domain||Description|
|phy_txdetectrx||1||Input||pclk||Tells the PHY to perform receiver detection when this
signal is logic High and POWERDOWN is in P1 low power state. Receiver
detection is complete when phystatus asserts for one pclk cycle. The
status of receiver detection is indicated in rxstatus when phystatus is
logic High for one pclk cycle.
|phy_txelecidle||1||Input||pclk||Forces the tx[p/n] to electrical idle when this signal is logic High. During electrical idle, tx[p/n] are driven to the DC common mode voltage. Per-lane.|
|phy_txcompliance||1||Input||pclk||Sets the running disparity to negative when this signal is logic High. Used when transmitting the PCIe compliance pattern. Per-lane.|
|phy_rxpolarity||1||Input||pclk||Requests the PHY to perform polarity inversion on the received data when this signal is logic High. Per-lane.|
|phy_powerdown[1:0]||2||Input||pclk||Request PHY to enter power saving state or return to
normal power state. Power management is complete when PHYSTATUS asserts
for one PCLK cycle.
P2 not supported.
|phy_rate[1:0]||2||Input||pclk||Request the PHY to perform a dynamic rate change. Rate change is
complete when PHYSTATUS asserts for one PCLK cycle. rxvalid, rxdata, and
rxstatus must be ignored while the PHY is in rate change.
In the simulation mode (PHY_SIM_EN = TRUE), PHY status assertion takes about 45 us for Gen3 speed change.