GT Specific Interface Ports - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)

Document ID
PG239
Release Date
2022-06-03
Version
1.0 English
Table 1. GT Specific Ports For UltraScale+ Devices Only
Name Width I/O Clock Domain Description
gt_gtpowergood 1 Output async GT power good indicator, connects to GTPOWERGOOD on transceiver channel primitives. Per Lane. This signal must be connected to the CE pin of the BUFG_GT that is driven by IBUFDS_GTE4(ref clock). (Make sure that all BUFG_GTs driven by the IBUFGS_GTE4 have the same CE/CLR pins)
gt_drpaddr 10 Input refclk GT Wizard DRP address. Per-lane
gt_drpen 1 Input refclk GT Wizard DRP Enable. Per-lane
g_drpwe 1 Input refclk GT Wizard DRP write/read. Per-lane
gt_drpdi 16 Input refclk GT Wizard DRP data in. Per-lane
gt_drprdy 1 Output refclk GT Wizard DRP ready. Per-lane
gt_drpdo 16 Output refclk GT Wizard DRP data out. Per-lane