The Xilinx® PCIe PHY IP is a building block IP that allows for a PCI Express® MAC to be built as soft IP in the FPGA fabric.
The Vivado® IP catalog does not allow generation of this IP for all UltraScale™ and UltraScale+™ devices; however, if a device is selected and has the same transceiver type as the desired device (UltraScale GTH, UltraScale+ GTH or UltraScale+ GTY), the IP can then be migrated to the desired part.
Currently, the IP can be generated for the following devices:
- UltraScale+: ZU9EG (GTH), VU3P (GTY), and VU9P(GTY).
- UltraScale: KU040 (GTH), KU115 (GTH), VU440 (GTH), and VU440 ES2 (GTH).
- When the IP is generated for a VU440 ES2 device, this IP should not be migrated to other devices.
- While some UltraScale devices contain GTYs, this IP does not support GTY in the UltraScale family.