Following is the example design operation:
- The example design expects the system reset to be received from the link partner.
- You have an additional option to override the system reset using
sys_rst_overrideprovided in the example design. This can be connected to any I/O on the board, such as a switch pin.
- The TX and RX electrical idle is High at this point.
- The design waits for the reset sequence to finish. For more information on the reset sequence, see Resets.
- The transceiver provides the
phystatus_rstwhich indicates that the PHY is ready. Make sure the PCIe MAC is connected to this output from the PHY.
- The design now waits for
phystatuson all lanes.
- Based on your selection of
phyrate(either Gen1, Gen2, Gen3 or Gen4), the design changes to the desired speed.