Product Specification - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)

Document ID
PG239
Release Date
2022-06-03
Version
1.0 English

The Xilinx® PCIe PHY IP core internally instantiates the GTY/GTH transceiver block model, which is highly configurable and tightly integrated with the programmable logic resources.

Note: UltraScale devices only support the GTH transceiver block model.