RX Data Signals for Ultrascale Devices Interface Ports - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)

Document ID: PG239
Release Date: 2022-06-03
Version: 1.0 English

Table 1. RX Data Signals for UltraScale Devices
Port Name	Width	I/O	Clock Domain	Description
phy_rx[p/n]	1	Input	Serial	The differential receiver inputs to the PHY. Per-lane.
phy_rxdata[31:0]	32	Output	pclk	PIPE data output from receiver. Bits[31:16] are used for Gen3 only and must be ignored in Gen1 and Gen2. Per-lane.
phy_rxdatak[1:0]	2	Output	pclk	Indicates whether RXDATA is control or data. Gen1 and Gen2 only. Per-lane. 0b: Data 1b: Control
phy_rxdata_valid	1	Output	pclk	This signal allows the PHY to instruct the MAC to ignore RXDATA for one pclk cycle. When logic High, this indicates to use RXDATA. When logic Low, this indicates to ignore RXDATA for one pclk cycle. Gen3 only. Per-lane.
phy_rxstart_block	1	Output	pclk	This signal allows the PHY to tell the MAC the starting byte for a 128b block. The starting byte for a 128b block must always start at bit [0] of RXDATA. Gen3 only. Per-lane.
phy_rxsync_header[1:0]	2	Output	pclk	Provide the sync header for the MAC to use the next 128b block. The MAC reads this value when the RXSYNC_BLOCK is asserted. Gen3 only. Per-lane.