To successfully reset UltraScale GTH for PCIe® applications, the recommended PCIe reset scheme should be used.
- It is recommended that the MAC or upper layer reset the PHY after power-on and fatal error conditions.
- The reference clock must be stable during reset.
- Once system reset is detected and synchronized, the PHY must assert
The following is an example of a x1 PCIe reset procedure:
- Stay in IDLE state until system reset is released.
- Assert [CPLL/QPLL]
- Release [CPLL/QPLL]
resetand wait for [CPLL/QPLL]
lockto go active-High.
- Release [TX/RX]
progdivresetand wait for [TX/RX]
progdivresetdoneto go active-High.
- Release GT[TX/RX]
reset, assert [TX/RX]
userrdyand wait for [TX/RX]
resetdoneto go active-High.
- Start TX SYNC alignment. Extend
- Wait for TXSYNC alignment to be done.
- Wait for
phystatusto get deasserted.
- Connect the
phystatus_rstoutput (communicates the completion of reset sequence) from the PHY to the PCIe MAC.
- PCIe MAC reset is complete.