Simulating the Example Design - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)
Document ID
PG239
Release Date
2022-06-03
Version
1.0 English

The example design provides a quick method to simulate and observe the behavior of the core generated using the Vivado® Design Suite.

The currently supported simulators are:

  • Vivado simulator (default)
  • Mentor Graphics Questa Advanced Simulator
  • Cadence Incisive Enterprise Simulator (IES)
  • Synopsys Verilog Compiler Simulator (VCS)

The simulator uses the example design test bench and test cases provided along with the example design for the design configuration.

For any project (PCIe PHY IP core) generated out of the box, the simulations using the default Vivado simulator can be run as follows:

  1. In the Sources Window, right-click the example project file (.xci), and select Open IP Example Design.

    The example project is created.

  2. In the Flow Navigator (left-hand pane), under Simulation, right-click Run Simulation and select Run Behavioral Simulation.
    Important: The post-synthesis and post-implementation simulation options are not supported for the PCIe PHY.

    After the Run Behavioral Simulation Option is running, you can observe the compilation and elaboration phase through the activity in the Tcl Console, and in the Simulation tab of the Log Window.

  3. In Tcl Console, type the run all command and press Enter. This runs the complete simulation as per the test case provided in example design test bench.

    After the simulation is complete, the result can be viewed in the Tcl Console.

In Vivado IDE, change the simulation settings as follows:

  1. In the Flow Navigator, under Simulation, select Simulation Settings.
  2. Set the Target simulator to QuestaSim/ModelSim Simulator, Incisive Enterprise Simulator (IES), or Verilog Compiler Simulator.
  3. In the simulator tab, select Run Simulation > Run behavioral simulation.
  4. When prompted, click Yes to change and then run the simulator.

The simulation environment provided with the PCIe PHY IP core performs rate change operation in the same sequence as described in the Overview. The simulation environment has the target speed set to Gen3.