The following features are not supported in the core:
- Lane 0 (master) must not be powered down or de-activated.
- Per-lane power down is not supported.
- P0s low power state is not supported when the max speed is configured as Gen3 or Gen4.
- P2 low power state is not supported.
- Bypassing the RX elastic buffer is not supported.
- Gen3 and Gen4 equalization settings are not preserved after the rate change.
- PCIe PHY does not check or monitor for PIPE protocol errors.
- PCIe beacon transmit and receive is not supported.
- The UltraScale+ Gen4 configuration does not support RX Lane Margining.