This register controls the operation of the core.
• Bit of the Control register, ap_start , kicks off the core from software. Writing 1 to this bit, starts the core to generate a video frame.
• Bit of the Control register, ap_done , indicates when the IP has completed all operations in the current transaction. A logic 1 on this signal indicates that the IP has completed all operations in this transaction.
• Bit of the Control register, ap_idle , signal indicates if the IP is operating or idle (no operation). The idle state is indicated by logic 1. This signal is asserted low once the IP starts operating. This signal is asserted high when the IP completes operation and no further operations are performed.
• Bit of the Control register, ap_ready , signal indicates when the IP is ready for new inputs. It is set to logic 1 when the IP is ready to accept new inputs, indicating that all input reads for this transaction are completed. If the IP has no operations in the pipeline, new reads are not performed until the next transaction starts. This signal is used to make a decision on when to apply new values to the input ports and whether to start a new transaction.
• Bit of the Control register, is for flushing pending AXI transactions. This bit should be set and held (until reset) by software to flush pending transactions. When this is set, the hardware is expecting a hard reset.
• Bit of the Control register is the flush status bit and is asserted when the flush is done.
• Bit of the Control register, auto_restart , can be set to enable the auto-restart mode. Thereafter, the IP restarts automatically at the end of each transaction.