If optional layers are enabled and configured as "Memory", there are certain requirements that must be taken care of while programming the core.
1. The core itself does not have a data realignment engine and therefore the application software must align the layer memory addresses before writing to the registers. The alignment requirement is specified below, and makes sure that the start address is aligned with the width of the memory interface.
2 × Pixels per Clock × 4 Bytes
2. When setting up the memory layer window, also the stride (in bytes) must be aligned as above to make sure that every row of pixels starts at an aligned memory location. To compute the stride from a window width in pixels the following equation can be used.
Stride in Bytes ≥ (Width × Bytes per Pixel);
Bytes per pixel varies per video in memory format, and is described in the section detailing the memory mapped AXI4 interface. Note that padding bytes are sometimes necessary (hence the ≥ in the equation) to make sure that every row of pixels starts at an address that is aligned with the size of the data on the memory mapped interface.
3. Layer Window Start Horizontal Position and Width must be a multiple of Pixels per Clock as selected in the Vivado Integrated Design Environment (IDE) for this core.