Synthesizable Example Design - 5.2 English

PG243 Video Mixer

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5.2 English

The difference between the Synthesizable design and the Simulation example design is the use of a microprocessor instead of the AXI VIP core as AXI4 master. In addition, the synthesizable design uses the MIG IP core for DDR memory access. The locked port of AXI4-Stream to Video Out is connected to axi_gpio_lock core and the processor polls the corresponding register for a sign that the test passed. This Figure shows a synthesizable example design.

Figure 5-2: Synthesizable Example Block Design

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The synthesizable example design requires both Vivado and Xilinx® Vitis™ tools.

The first step is to run synthesis, implementation and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware . In the window, select Include bitstream , select an export directory and click OK to create an XSA project.

Figure 5-3: Export Hardware

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The remaining work is performed in the Xilinx Vitis tool. The Video Mixer example design file can be found in the following Vitis directory:


The example application design source files (contained within examples folder) are tightly coupled with the v_mix example design available in Vivado IP catalog.

Perform the following steps to get the .elf file from the Vitis application.

1. Open the Vitis application.

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2. Select the new application project in File > New Application Project .

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3. Select a platform to create the project.

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4. Select the required xsa.

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5. Click Next .

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6. Name the application.

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7. Select the processor and click Next .

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8. Select the empty application.

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9. Import the required files.

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10. Build the project.

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