When the MI is wider than the SI, upsizing is performed, and in the resulting transaction issued to the MI side, the number of data beats is reduced accordingly.
•For Writes, data merging occurs on the W-channel between the SI and MI.
•For Reads, data serialization occurs on the R-channel between the MI and SI.
The AXI SmartConnect core replicates the rresp from each MI-side (wide) input read data beat onto the rresp of each of the resulting SI-side (narrow) output data beats.
Transactions always remain fully packed when upsizing both writes and reads. Data packing is not disabled in response to the modifiable bit (awcache[1] or arcache[1]) of the address transfer. Upsizing does not cause transaction splitting.