Additional Resources and Legal Notices - 1.0 English

SmartConnect (PG247)

Document ID
PG247
Release Date
2022-10-19
Version
1.0 English

Additional Resources and Legal Notices

Xilinx Resources

For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.

References

These documents provide supplemental material useful with this product guide:

1.AXI4-Stream LogiCORE IP Interconnect Product Guide (PG085)

2.Arm AMBA AXI Protocol v2.0 Specification (IHI 0022CI)

3.FIFO Generator LogiCORE IP Product Guide (PG057)

4.Vivado Design Suite User Guide: Designing with IP (UG896)

5.Vivado Design Suite User Guide: Getting Started (UG910)

6.Vivado Design Suite User Guide: Designing IP Subsystems using IP integrator (UG994)

7.Vivado Design Suite User Guide: Logic Simulation (UG900)

8.Vivado Design Suite User Guide: Programming and Debugging (UG908)

9.AXI Bus Functional Models User Guide (UG783)

10.Xilinx AXI Reference Guide (UG1037)

11.Zynq-7000 SoC (Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics (DS187)

12.Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics (DS191)

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

10/19/2022

1.0

Added Multi-threading and downsizing note in Width Conversion.

04/21/2022

1.0

Added non-GUI Advanced Properties set via TCL command-line.

Added MI Multi-threading feature.

Added SmartConnect 1x1 Mode.

02/03/2020

1.0

Added description to Feature Summary.

Updated AXI SmartConnect Core Limitations.

Added table note #1 to Table: AXI SmartConnect Core Master I/O Signals.

Updated Use of ID Signals.

Added AXI4-to-AXI3 Conversion.

Added Exclusive Access.

Added note in How to Adjust SmartConnect?.

Added Advanced Property table notes in Functional View – Advanced Properties and Timing View – Advanced Properties.

Updated description in Upgrading Exceptions and Upgrading Instructions.

Updated description in Feature Comparison.

03/04/2019

1.0

Updated: AXI SmartConnect Core Limitations; Design Parameters; Upgrading Guidelines and Controlling Performance in Appendix A; Updated Table: Snn_Entry Advanced Properties, Table: Snn_Buffer and Mnn_Buffer Advanced Properties, and Table: Mnn_Exit Clocking Advanced Properties.

12/20/2017

1.0

Added Migration instructions.

Added Pipelining/Constraints content.

10/04/2017

1.0

Tables 3-6 and 3-7: Added Per-channel Asynchronous Clock Crossing Stages.

Updated description for downsizing to an AXI4-Lite slave.

04/05/2017

1.0

ADVANCED_PROPERTIES added to Design Parameters.

Protocol Conversion section: Additional information provided on downsizing to AXI4-Lite slave.

10/05/2016

1.0

Support for FIXED Burst type transactions removed.

HAS_ARESETN added to Design Parameters.

05/10/2016

1.0

Initial Xilinx release as product guide release.

 

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