Internal Payload Buffering - 1.0 English

SmartConnect (PG247)

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1.0 English

Transfers on all five AXI channels are buffered on both the SI and MI-sides of the central switching plane to support high throughput and reduce throttling. By default, buffers on the SI and MI sides for each channel are implemented using 32-deep distributed RAM. The depths for each buffer can be modified using the Advanced Properties. The buffer type automatically changes to block RAM when a depth of 512 or greater is specified.

The buffers on the SI side of the AW and AR channels can optionally operate in packet mode to avoid full/empty stalls within bursts.

For Write packet mode, the issuing of the AW channel transfer from the buffer is delayed until the entire write burst has been stored in the W-Channel buffer (wlast is received), therefore avoiding stalling due to a slow write data source. To avoid deadlock, the AW command is alternatively issued whenever the SI receives a number of data beats of the same burst that exceeds the total SI-side buffer capacity.

For read packet mode, the issuing of the AR channel transfer is delayed until the R-Channel buffer has enough vacancy to store the entire burst, according to ARLEN (vacancy is defined as the amount of free space in the R channel FIFO that has not already been committed by previously issued AR commands). This avoids stalling due to a slow read destination. The first AR command received when there are no outstanding reads is always issued immediately. Beyond that, delaying of AR channel commands begins only after the data accumulated in the R channel FIFO has reached a designated threshold, and therefore does not contribute to read command latency.