•Up to 16 Slave Interfaces (SI) and up to 16 Master Interfaces (MI) per instance.
°Supports connecting one SI to up to 64 AXI4-Lite MI.
•Instances of SmartConnect can be cascaded to interconnect a larger number of masters/slaves or for organizing the interconnect topology.
•AXI Protocol compliant. Each SI and MI of SmartConnect can be connected to a master or slave IP interface of type AXI3, AXI4 or AXI4-Lite.
°Transactions between interfaces of different protocol types are automatically converted by SmartConnect.
°Burst transactions are automatically split, as required, to remain AXI compliant.
•Interface Data Widths (bits):
°AXI4 and AXI3: 32, 64,128, 256, 512, or 1024.
°AXI4-Lite: 32 or 64-bit.
•Transactions between interfaces of different data widths are automatically converted by SmartConnect.
•Supports multiple clock domains (the IP provides one clock pin per domain).
°Transactions between interfaces in different clock domains are automatically converted by SmartConnect.
•Address width: Up to 64 bits:
°SmartConnect decodes up to 256 total address range segments.
•User defined signals up to 512 bits wide per channel.
°User signals on any AXI channel are propagated regardless of internal transaction conversions.
•Support for Read-only and Write-only masters and slaves, resulting in reduced resource utilization.
•Supports multiple outstanding transactions:
°Supports connected masters with multiple reordering depth (ID threads).
°Supports write response reordering, Read data reordering, and Read Data interleaving.
°Multi-threaded traffic (masters issuing multiple ID threads) is supported across the interconnect topology regardless of internal transaction conversions, including data width conversion and transaction splitting.
•Single-Slave per ID method of cyclic dependency (deadlock) avoidance.
°For each ID thread issued by a connected master, the SmartConnect allows one or more outstanding transactions to only one slave device for Writes and one slave device for Reads, at a time.
•Multiple parallel pathways along all AXI channels when connected to multiple masters and multiple slaves:
°Each AXI channel has independent destination-side arbitration. Transfers from two or more source endpoints to separate destination endpoints can occur concurrently, for any AXI channel.
°Round-robin arbitration for each of the AW, AR, R and B channels. (W-channel transfers follow the same order as AW-channel arbitration, per AXI protocol rules.)
•Supports back-to-back transfers (100% duty cycle) on any AXI channel:
°Single data-beat transactions can traverse the SmartConnect at the same bandwidth as multi-beat bursts.
•Supports TrustZone security for each connected slave:
°If configured as a secure address segment, only secure AXI accesses are permitted according to the AXI arprot or awprot signal.
°Any non-secure accesses are blocked and the AXI SmartConnect core returns a decerr response to the connected master.
•Supports Exclusive Access between connected masters and slaves.
•Internally resynchronized reset:
°One aresetn input per IP.
AXI SmartConnect is general-purpose, and is typically deployed in all systems using AXI memory-mapped transfers.
These limitations apply to the AXI SmartConnect core:
•SmartConnect unconditionally packs all multi-beat bursts to fill the interface data-width.
SmartConnect SI interfaces accept narrow bursts, in which the arsize or awsize signal indicates data units which are smaller than the interface data-width. But such bursts are always propagated through the SmartConnect and its MI interfaces fully packed. The modifiable bit of the AXI arcache or awcache signal does not prevent packing.
When a single-beat transaction (arlen = 0 or awlen = 0) is received and the arsize/awsize signal indicate a data unit smaller than the data-width of the targeted MI, the narrow size of the single-beat transaction is preserved and propagated to the MI, so that the range of address locations originally specified by the master are not exceeded.
•SmartConnect converts all WRAP type bursts into INCR type. SmartConnect SI interfaces accept all protocol-compliant WRAP bursts, beginning at any target address. But such bursts are always converted to a single INCR burst beginning at the wrap address. This may increase response latency of unaligned read wrap bursts.
•SmartConnect does not support FIXED type bursts. Any FIXED burst transaction received at the SmartConnect SI is blocked and a DECERR response is returned to the master.
•By default, SmartConnect does not propagate ID values on the MI to the connected slave. IDs received at an SI interface are used internally by SmartConnect for reordering and response routing. These are stored internally and restored during response transfers.
°AXI ID signals cannot be used in the system to identify the master originating an AXI transaction. Instead, Xilinx recommends using the aruser and awuser signals to convey master identification information, as needed.
•The AXI SmartConnect core does not support discontinued AXI3 features:
°Atomic locked transactions: This feature was retracted by the AXI4 protocol. A locked transaction is changed to a non-locked transaction and propagated by the MI.
°Write interleaving: This feature was retracted by AXI4 protocol. AXI3 master devices must be configured as if connected to a slave with a Write interleaving depth of one.
•By default, all arbitration on all AXI channels is round-robin.
•AXI4 Quality of Service (arqos and awqos) signals do not influence arbitration priority. QoS signals are propagated from SI to MI.
•SmartConnect neither propagates nor generates the AXI4 arregion or awregion signal.
•SmartConnect does not support independent reset domains. If any master or slave device connected to SmartConnect is reset, then all connected devices must be reset concurrently.
•SmartConnect does not propagate the AXI Low power interface (C-channel) signals.
•SmartConnect does not time out if the destination of any AXI channel transfer stalls indefinitely. All connected AXI slaves must respond to all received transactions, as required by AXI protocol.
•SmartConnect provides no address remapping.
•SmartConnect does not include conversion or bridging to non-AXI protocols, such as APB.
This Xilinx® LogiCORE IP module is provided at no additional cost with the Xilinx Vivado Design Suite under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information about pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative.