Resets - 1.0 English

SmartConnect (PG247)

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1.0 English

The SmartConnect IP has one active-low reset input (aresetn). The reset input is internally resynchronized to each of the clock domains connected to the IP.

If no soft reset is required beyond power-on, the aresetn pin may be disabled (HAS_ARESETN=0). All internal state logic will automatically be initialized during power-up.

The SmartConnect core deasserts all valid and ready outputs during the power-on reset cycle and shortly after aresetn is sampled active, and for the duration of the aresetn pulse.

AXI protocol requires that all connected masters also deassert all valid outputs during reset (until after aresetn is sampled inactive). Slaves must not assert response-channel valid outputs until after they receive a command from a master. It is also strongly recommended that slave IP deassert their ready outputs until after reset. This avoids inadvertently signaling a transfer completion in case a connected IP recovers from reset during an earlier cycle and asserts its valid.

There is no requirement that the assertion or deassertion of aresetn be observed during the same cycle or in any relative order among SmartConnect and its connected masters and slaves. It is, however, required that the cycles during which reset is applied to SmartConnect and all its connected masters and slaves overlap.

SmartConnect does not support independent reset domains. If any master or slave device connected to SmartConnect is reset, then all connected devices must be reset concurrently.


RECOMMENDED:   As a general design guideline, Xilinx recommends asserting system aresetn signals for a minimum of 16 clock cycles (of the slowest aclk input), as that is known to satisfy the preceding reset requirement.