Timing View – Advanced Properties - 1.0 English

SmartConnect (PG247)

Document ID: PG247
Release Date: 2022-10-19
Version: 1.0 English

Table 3-5: Snn_Entry Advanced PropertiesCONFIG.ADVANCED_PROPERTIES dictionary keys: __view__ timing Snn_Entry
Name	Description	Format/Range/Dependencies
MMU_REGSLICE⁽¹⁾	MMU Register Slice Enables or disables a register slice at the outer boundary of the SmartConnect port. The exterior register slice is enabled by default but you can disable it via this advanced property to reduce area and latency (if it is known that the IP attached to the SmartConnect port is suitably pipelined).	Type: Integer Values: 0,1 Default: 1
TR_REGSLICE⁽¹⁾	Transaction Regulator Register Slice Enables or disables a register slice on the interior pathway of the port's entry pipeline. The interior register slice is enabled by default but you can disable it to reduce area and latency (if it is known that no adverse effect on timing closure will occur).	Type: Integer Values: 0,1 Default: 1
Notes: 1.This Advanced Property is ignored when SmartConnect is configured in AXI4-Lite Low-Area Mode. When all of the endpoint slaves connected to the MI-side of the SmartConnect are 32-bit-wide AXI4-Lite slaves, the SmartConnect Hierarchical IP uses Low-Area Mode to optimize for Area at the expense of performance. In Low-Area Mode, all optional register slices are disabled. Instantiate and connect an AXI Register Slice core to any SI or MI of the SmartConnect, enabled per-channel as needed, if you observe a timing-critical path through the SI or MI.

Table 3-6: Snn_Buffer Advanced PropertiesCONFIG.ADVANCED_PROPERTIES dictionary keys: __view__ timing Snn_Buffer
Name	Description	Format/Range/Dependencies
AR_SLR_PIPE AW_SLR_PIPE R_SLR_PIPE W_SLR_PIPE B_SLR_PIPE	Per-channel SLR Pipeline Control Specifies number of pipeline stages that improve SLR-crossing in the corresponding channel's data buffer. See Constraining the Core for information on associated placement constraints to ensure the SLR crossing pipeline flops are placed correctly.	Type: Integer Values: 0..3 Default: 0
AR_M_PIPE AW_M_PIPE W_M_PIPE	Per-channel Payload Pipeline Control Enables or disables pipeline stages for channel payloads between the channel's Snn_Buffer and Switchboard. The interior register slice is enabled by default but you can disable it to reduce area and latency (if it is known that no adverse effect on timing closure will occur).	Type: Integer Values: 0..3 Default: 0
AR_M_SEND_PIPE AW_M_SEND_PIPE W_M_SEND_PIPE	Per-channel Handshake Pipeline Control Enables or disables pipeline stages for channel handshakes between the Snn_Buffer and SmartConnect's channel switchboards.	Type: Integer: Values: 0,1 Default: 1
AR_SYNC_STAGES AW_SYNC_STAGES R_SYNC_STAGES W_SYNC_STAGES B_SYNC_STAGES	Per-channel Asynchronous Clock Crossing Stages Specifies the number of synchronization stages used in asynchronous clock domain conversion.	Type: Integer: Values: 2..8 Default: 3

Table 3-7: Mnn_Buffer Advanced PropertiesCONFIG.ADVANCED_PROPERTIES dictionary keys: __view__ timing Mnn_Buffer
Name	Description	Format/Range/Dependencies
AR_SLR_PIPE AW_SLR_PIPE R_SLR_PIPE W_SLR_PIPE B_SLR_PIPE	Per-channel SLR Pipeline Control Specifies number of pipeline stages that improve SLR-crossing in the corresponding channel's data buffer. See Constraining the Core for information on associated placement constraints to ensure the SLR crossing pipeline flops are placed correctly.	Type: Integer: 0..3 Default: 0
R_M_PIPE B_M_PIPE	Per-channel Payload Pipeline Control Enables or disables pipeline stages for channel payloads between the channel's Snn_Buffer and Switchboard The interior register slice is enabled by default but you can disable it to reduce area and latency (if it is known that no adverse effect on timing closure will occur).	Type: Integer: 0..3 Default: 0
R_M_SEND_PIPE B_M_SEND_PIPE	Per-channel Handshake Pipeline Control Enables or disables pipeline stages for channel handshakes between the Snn_Buffer and SmartConnect's channel switchboards.	Type: Integer: 0, 1 Default: 1
AR_SYNC_STAGES AW_SYNC_STAGES R_SYNC_STAGES W_SYNC_STAGES B_SYNC_STAGES	Per-channel Asynchronous Clock Crossing Stages Specifies the number of synchronization stages used in asynchronous clock domain conversion.	Type: Integer: Values: 2..8 Default: 3

Table 3-8: Switchboard (SW0) Advanced PropertiesCONFIG.ADVANCED_PROPERTIES dictionary keys: __view__ timing SW0
Name	Description	Format/Range/Dependencies
AR_M_PIPE AW_M_PIPE R_M_PIPE W_M_PIPE B_M_PIPE	Per-channel Payload Pipeline Control Enables pipeline stages on the egress of the given channel switchboard.	Type: Integer: 0..3 Default: 1
AR_S_PIPE AW_S_PIPE R_S_PIPE W_S_PIPE B_S_PIPE	Per-channel Payload Pipeline Control Enables pipeline stages on the ingress of the given channel switchboard.	Type: Integer: 0..3 Default: 0

Table 3-9: Mnn_Exit Advanced PropertiesCONFIG.ADVANCED_PROPERTIES dictionary keys: __view__ timing Mnn_Exit
Name	Description	Format/Range/Dependencies
REGSLICE⁽¹⁾	Exit Register Slice Enables or disables a register slice at the outer boundary of the SmartConnect port. The exterior register slice is enabled by default but you can disable it via this advanced property to reduce area and latency (if it is known that the IP attached to the SmartConnect port is suitably pipelined).	Type: Integer: 0, 1 Default: 1
Notes: 1.This Advanced Property is ignored when SmartConnect is configured in AXI4-Lite Low-Area Mode. When all of the endpoint slaves connected to the MI-side of the SmartConnect are 32-bit-wide AXI4-Lite slaves, the SmartConnect Hierarchical IP uses Low-Area Mode to optimize for Area at the expense of performance. In Low-Area Mode, all optional register slices are disabled. Instantiate and connect an AXI Register Slice core to any SI or MI of the SmartConnect, enabled per-channel as needed, if you observe a timing-critical path through the SI or MI.