Upgrading Instructions - 1.0 English

SmartConnect (PG247)

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1.0 English

Use the following steps to upgrade from AXI Interconnect v2 to SmartConnect v1.0:

1.Configure the number of SIs and MIs to match AXI Interconnect being replaced.

2.Set the number of clock inputs to the number of unique clock signals that were connected to AXI Interconnect. Do not include additional clock input pins to which the same clock signal(s) were connected.

3.If your AXI Interconnect connected to endpoint slaves that were all 32-bit AXI4-Lite, then SmartConnect will automatically use its area-optimized mode. There is no user setting required for this feature.

4.You cannot specify register pipelining and/or FIFO buffering at this time. You can set them using the SmartConnect Advance Properties only after connecting the SmartConnect instance to all endpoint logic and running Validation. Otherwise, wait until after you review your implementation results using the default settings. The deployment of pipelines and FIFO buffers in SmartConnect is fundamentally different from that in AXI Interconnect.

5.After customizing, reconnect all SI and MI ports to their AXI endpoints.

6.Reconnect the SmartConnect aclk and aresetn inputs to the same signals as in AXI Interconnect.

7.Connect all remaining clock signals (if any) to any of the additional clock inputs. (SmartConnect automatically detects the clock domain associated with each SI and MI interface connection.)

8.Do not connect any other reset signals that were previously connected to AXI Interconnect. SmartConnect will internally re-synchronize to each SI/MI clock domain.

9.If your AXI Interconnect used fixed priority to lessen the impact of lower-priority masters on high-performance traffic, then you could likely achieve similar results by specifying a low positive value for Limit Read/Write Length (Advanced Properties) for lower-priority SI interfaces. This forces any bursts longer than the specified value to get split into a series of shorter bursts, effectively lowering the transaction's service rate during SmartConnect round-robin arbitration.

10.If any of the AXI slave devices in your application relies on reading the ID value issued by AXI Interconnect to positively identify the master issuing the transaction, this capability is no longer supported using the ID signal when using SmartConnect. Instead, Xilinx recommends using the awuser/aruser signals to transmit source identification constants to endpoint slaves. SmartConnect automatically compresses or eliminates AXI ID signals when not needed to control response reordering among multi-threaded traffic.

11.If your AXI Interconnect used packet-mode FIFOs to prevent data channel stalling due to buffer overrun/underrun, refer to the Packet Write/Read Threshold (Advanced Properties) for the corresponding SmartConnect functionality.