The transaction ID signals that propagate from SIs to MIs (awid and arid) and back again (bid and rid), control both the routing of response transfers, and the ordering of AXI transfer propagation within the SmartConnect and among a collection of cascaded SmartConnect instances.
Endpoint master devices can optionally output awid and arid signals that the master device can use to select among multiple threads of transactions (as though the master IP core was comprised of multiple master devices internally). The reordering depth is the total number of ID values that can be generated by a master, as determined by the width of the master’s ID signals. Master devices with a reordering depth of one do not need ID signals on their interface. The width of ID signals may vary among SIs.
AXI transaction ordering rules are as follows:
•There are no rules regarding the relative ordering between write transactions and read transactions.
•Transactions (of each direction) belonging to the same thread must be returned in order.
•Transactions (of each direction) among different threads can be returned out-of-order.
All response transfers on R or B channels of an SI contain rid or bid values that match the arid or awid (if present) of the original commands issued by the master on the AW or AR channel of the SI. However, the SmartConnect modifies the original ID values, such as to differentiate among transactions originating at different SIs, and therefore does not preserve these original ID values when propagating transactions to the MI. By default, SmartConnect does not propagate ID signals to a connected endpoint slave. Consequently, endpoint slaves are required by protocol to return all transaction responses in order. ID signals are exchanged among cascaded SmartConnect instances so as to support multi-threading across the entire interconnect topology.
When an SI is configured in single-ordered mode (number of ID threads = 1), all IDs received on the SI are stored and retrieved locally. The connected master may still issue multiple outstanding transactions, and the transaction IDs (if any) may have any value. However, all transactions issued by the master are propagated and returned in order. This results in the most resource-efficient implementation.
If an SI is configured as multi-threaded (supporting a number of ID threads > 1), then transaction ID values received from the connected master are dynamically re-mapped to an ID of equal or smaller width. This reduces the total number of ID threads monitored by the SmartConnect, resulting in a more resource-efficient implementation. When a multi-threaded master issues read or write transactions to different endpoint slaves using different ID values, the responses might be returned out-of-order.
If there are multiple SIs, the SmartConnect makes ID values among all SIs unique before propagating to the MI. The SmartConnect core appends a constant unique master-ID value to the re-mapped thread-ID from the SI (if any). The master-ID values are assigned by the tools. Master IP in the Xilinx IP catalog or packaged by the user may include metadata indicating the master's reordering depth, which is the number of ID threads that should be tracked by SmartConnect for the connected SI. By default, the SI is configured in single-ordered mode.
An advanced mode of SmartConnect, called "MI Multi-threading", allows varying ID signals to propagate to connected endpoint slave devices, allowing those slaves to respond out-of-order. When enabled (see Advanced Properties), a limited range of ID values are generated at each endpoint MI of SmartConnect to represent transactions originating with different IDs at an endpoint SI and/or originating from different SIs. The lifespan of a generated ID value ends when all transactions belonging to the same ID thread complete at the MI; then that ID value becomes available to be reused by a subsequent transaction thread arriving at the MI. There is no correlation of ID values between write and read transaction on the same MI, or between transactions issued among different MIs. By default, the MI's reordering depth (number of ID values) is set automatically based on the ID-width of slave's SI, and other factors. Increasing the reordering depth of each MI increases its resource cost. MI multi-threading is supported regardless of any conversions (including data-width conversion and transaction splitting) that may occur along the pathway across a SmartConnect or collection of cascaded SmartConnects.
AXI ID signals cannot be used in the system to identify the master originating an AXI transaction. Instead, Xilinx recommends using the aruser and awuser signals to convey master identification information, as needed.