User-defined signals on the W and R channels (wuser and ruser) are always formatted in terms of user bits per byte of data. As data is serialized or merged during downsizing or upsizing, the bit-lanes associated with each byte of data travel with the data bytes. When an SI and MI have the same number of user bits per byte, the total widths of their wuser and ruser signals remain in proportion to their data widths, and all user bits will propagate through the intervening width conversion. When the user bits per byte differ between the SI and MI, padding or truncation of high-order user bit positions is performed on a per-byte-lane basis. Propagation of wuser and ruser signals by SmartConnect is suitable for transporting byte-wise parity information between a data source that generates parity and a data destination that detects parity errors. The SmartConnect neither generates nor detects parity.
The propagation of user bits on R and W channels of an AXI4 memory-mapped interface, when traversing width conversion, is not prescribed by the AXI4 protocol specification. However, it is defined for the AXI4-Stream protocol. Xilinx SmartConnect uses the same transformation for R and W channel width conversion as prescribed in the AXI4-Stream specification.
Width conversion does not affect the propagation of user signals on the AR, AW and B channels. However, when transactions are split as a result of downsizing or AXI3 protocol conversion, the entire user signal received on the AR or AW channel is replicated in all resulting transfers on the MI. Conversely, when multiple B-channel transfers received on the MI are consolidated as a result of a split write transaction, only the user signal received on the last of the consolidated B transfers is propagated to the SI; user information received on earlier B transfers is discarded.