Each of the SIs and MIs on the AXI SmartConnect core can be connected to a master or slave endpoint with a data width of 32, 64, 128, 256, 512, or 1024 bits. When a transaction at an SI targets an MI with a different data width, width conversion is automatically performed along the pathway. The internal data pathways that connect SIs to MIs vary in width.
All data width conversions support the propagation of ID signals between SmartConnect SI and MI to support multi-threading across the interconnect topology. Out-of-order response transfers resulting from multi-threaded traffic (if enabled) is managed by the width converters.
The width conversion transformations differ depending on whether the datapath width widens (upsizing) or narrows (downsizing) when moving from the SI toward the MI.
IMPORTANT: Multi-threading and downsizing cannot be used together. If this combination is detected, a critical warning is issued during the validate step in the IP integrator, and multi-threading is automatically disabled.