USXGMII Ethernet Subsystem Product Guide (PG251) - 1.2 English

Document ID: PG251
Release Date: 2022-12-08
Version: 1.2 English

USXGMII Ethernet Subsystem v1.2 Product Guide
IP Facts
Introduction
Features
Overview
Navigating Content by Design Process
Feature Summary
Licensing and Ordering
Product Specification
TX Data Path
RX Datapath
USXGMII at Lower Speeds
Auto-Negotiation
Clause 37 Auto-Negotiation Operation
Standards
Performance and Resource Utilization
Latency
Transmit Path Latency
Receive Path Latency
Port Descriptions
Transceiver Interface
AXI4-Stream Interfaces
AXI4-Stream Clocks and Resets
Transmit AXI4-Stream Interface
Data Lane Mapping
Normal Frame Transmission
Back to Back Continuous Transfers
Aborting a Transmission
Receive AXI4-Stream Interface
Data Lane Mapping
Normal Frame Reception
Frame Reception with Errors
AXI4-Stream Control and Status Ports
Miscellaneous Status/Control Signals
Statistics Interface Ports
Pause Interface
Pause Interface – TX
Pause Interface – RX
Register Space
AXI4-Lite Ports
Configuration Register Map
Status Register Map
Statistics Counters
Register Descriptions
Configuration Registers
GT_RESET_REG: 0000
RESET_REG: 0004
MODE_REG: 0008
CONFIGURATION_TX_REG1: 000C
CONFIGURATION_RX_REG1: 0014
CONFIGURATION_RX_MTU: 0018
TICK_REG: 0020
CONFIGURATION_REVISION_REG: 0024
CONFIGURATION_TX_TEST_PAT_SEED_A_LSB: 0028
CONFIGURATION_TX_TEST_PAT_SEED_A_MSB: 002C
CONFIGURATION_TX_TEST_PAT_SEED_B_LSB: 0030
CONFIGURATION_TX_TEST_PAT_SEED_B_MSB: 0034
CONFIGURATION_1588_REG: 0038
CONFIGURATION_TX_FLOW_CONTROL_REG1: 0040
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1: 0044
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2: 0048
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3: 004C
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4: 0050
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5: 0054
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1: 0058
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2: 005C
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3: 0060
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4: 0064
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5: 0068
CONFIGURATION_TX_FLOW_CONTROL_PPP_ETYPE_OP_REG: 006C
CONFIGURATION_TX_FLOW_CONTROL_GPP_ETYPE_OP_REG: 0070
CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_LSB: 0074
CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_MSB: 0078
CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_LSB: 007C
CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_MSB: 0080
CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_LSB: 0084
CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_MSB: 0088
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB: 008C
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB: 0090
CONFIGURATION_RX_FLOW_CONTROL_REG1: 0094
CONFIGURATION_RX_FLOW_CONTROL_REG2: 0098
CONFIGURATION_RX_FLOW_CONTROL_PPP_ETYPE_OP_REG: 009C
CONFIGURATION_RX_FLOW_CONTROL_GPP_ETYPE_OP_REG: 00A0
CONFIGURATION_RX_FLOW_CONTROL_GCP_PCP_TYPE_REG: 00A4
CONFIGURATION_RX_FLOW_CONTROL_PCP_OP_REG: 00A8
CONFIGURATION_RX_FLOW_CONTROL_GCP_OP_REG: 00AC
CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_LSB: 00B0
CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_MSB: 00B4
CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_LSB: 00B8
CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_MSB: 00BC
CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_LSB: 00C0
CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_MSB: 00C4
CONFIGURATION_USXGMII_AN: 00C8
USER_REG_0: 0184
USER_REG_1: 0188
CONFIGURATION_TX_PTP_LATENCY_ADJUST_REG: 0194
CONFIGURATION_RX_PTP_LATENCY_ADJUST_REG: 0198
Status Registers
STAT_TX_STATUS_REG1: 0400
STAT_RX_STATUS_REG1: 0404
STAT_STATUS_REG1: 0408
STAT_RX_BLOCK_LOCK_REG: 040C
STAT_TX_FLOW_CONTROL_REG1: 0450
STAT_RX_FLOW_CONTROL_REG1: 0454
STAT_AN_STATUS_REG1: 0458
STAT_RX_VALID_CTRL_CODE: 0494
Statistics Counters
STATUS_CYCLE_COUNT_LSB: 0500
STATUS_CYCLE_COUNT_MSB: 0504
STAT_RX_FRAMING_ERR_LSB: 0648
STAT_RX_FRAMING_ERR_MSB: 064C
STAT_RX_BAD_CODE_LSB: 0660
STAT_RX_BAD_CODE_MSB: 0664
STAT_TX_FRAME_ERROR_LSB: 06A0
STAT_TX_FRAME_ERROR_MSB: 06A4
STAT_TX_TOTAL_PACKETS_LSB: 0700
STAT_TX_TOTAL_PACKETS_MSB: 0704
STAT_TX_TOTAL_GOOD_PACKETS_LSB: 0708
STAT_TX_TOTAL_GOOD_PACKETS_MSB: 070C
STAT_TX_TOTAL_BYTES_LSB: 0710
STAT_TX_TOTAL_BYTES_MSB: 0714
STAT_TX_TOTAL_GOOD_BYTES_LSB: 0718
STAT_TX_TOTAL_GOOD_BYTES_MSB: 071C
STAT_TX_PACKET_64_BYTES_LSB: 0720
STAT_TX_PACKET_64_BYTES_MSB: 0724
STAT_TX_PACKET_65_127_BYTES_LSB: 0728
STAT_TX_PACKET_65_127_BYTES_MSB: 072C
STAT_TX_PACKET_128_255_BYTES_LSB: 0730
STAT_TX_PACKET_128_255_BYTES_MSB: 0734
STAT_TX_PACKET_256_511_BYTES_LSB: 0738
STAT_TX_PACKET_256_511_BYTES_MSB: 073C
STAT_TX_PACKET_512_1023_BYTES_LSB: 0740
STAT_TX_PACKET_512_1023_BYTES_MSB: 0744
STAT_TX_PACKET_1024_1518_BYTES_LSB: 0748
STAT_TX_PACKET_1024_1518_BYTES_MSB: 074C
STAT_TX_PACKET_1519_1522_BYTES_LSB: 0750
STAT_TX_PACKET_1519_1522_BYTES_MSB: 0754
STAT_TX_PACKET_1523_1548_BYTES_LSB: 0758
STAT_TX_PACKET_1523_1548_BYTES_MSB: 075C
STAT_TX_PACKET_1549_2047_BYTES_LSB: 0760
STAT_TX_PACKET_1549_2047_BYTES_MSB: 0764
STAT_TX_PACKET_2048_4095_BYTES_LSB: 0768
STAT_TX_PACKET_2048_4095_BYTES_MSB: 076C
STAT_TX_PACKET_4096_8191_BYTES_LSB: 0770
STAT_TX_PACKET_4096_8191_BYTES_MSB: 0774
STAT_TX_PACKET_8192_9215_BYTES_LSB: 0778
STAT_TX_PACKET_8192_9215_BYTES_MSB: 077C
STAT_TX_PACKET_LARGE_LSB: 0780
STAT_TX_PACKET_LARGE_MSB: 0784
STAT_TX_PACKET_SMALL_LSB: 0788
STAT_TX_PACKET_SMALL_MSB: 078C
STAT_TX_BAD_FCS_LSB: 07B8
STAT_TX_BAD_FCS_MSB: 07BC
STAT_TX_UNICAST_LSB: 07D0
STAT_TX_UNICAST_MSB: 07D4
STAT_TX_MULTICAST_LSB: 07D8
STAT_TX_MULTICAST_MSB: 07DC
STAT_TX_BROADCAST_LSB: 07E0
STAT_TX_BROADCAST_MSB: 07E4
STAT_TX_VLAN_LSB: 07E8
STAT_TX_VLAN_MSB: 07EC
STAT_TX_PAUSE_LSB: 07F0
STAT_TX_PAUSE_MSB: 07F4
STAT_TX_USER_PAUSE_LSB: 07F8
STAT_TX_USER_PAUSE_MSB: 07FC
STAT_RX_TOTAL_PACKETS_LSB: 0808
STAT_RX_TOTAL_PACKETS_MSB: 080C
STAT_RX_TOTAL_GOOD_PACKETS_LSB: 0810
STAT_RX_TOTAL_GOOD_PACKETS_MSB: 0814
STAT_RX_TOTAL_BYTES_LSB: 0818
STAT_RX_TOTAL_BYTES_MSB: 081C
STAT_RX_TOTAL_GOOD_BYTES_LSB: 0820
STAT_RX_TOTAL_GOOD_BYTES_MSB: 0824
STAT_RX_PACKET_64_BYTES_LSB: 0828
STAT_RX_PACKET_64_BYTES_MSB: 082C
STAT_RX_PACKET_65_127_BYTES_LSB: 0830
STAT_RX_PACKET_65_127_BYTES_MSB: 0834
STAT_RX_PACKET_128_255_BYTES_LSB: 0838
STAT_RX_PACKET_128_255_BYTES_MSB: 083C
STAT_RX_PACKET_256_511_BYTES_LSB: 0840
STAT_RX_PACKET_256_511_BYTES_MSB: 0844
STAT_RX_PACKET_512_1023_BYTES_LSB: 0848
STAT_RX_PACKET_512_1023_BYTES_MSB: 084C
STAT_RX_PACKET_1024_1518_BYTES_LSB: 0850
STAT_RX_PACKET_1024_1518_BYTES_MSB: 0854
STAT_RX_PACKET_1519_1522_BYTES_LSB: 0858
STAT_RX_PACKET_1519_1522_BYTES_MSB: 085C
STAT_RX_PACKET_1523_1548_BYTES_LSB: 0860
STAT_RX_PACKET_1523_1548_BYTES_MSB: 0864
STAT_RX_PACKET_1549_2047_BYTES_LSB: 0868
STAT_RX_PACKET_1549_2047_BYTES_MSB: 086C
STAT_RX_PACKET_2048_4095_BYTES_LSB: 0870
STAT_RX_PACKET_2048_4095_BYTES_MSB: 0874
STAT_RX_PACKET_4096_8191_BYTES_LSB: 0878
STAT_RX_PACKET_4096_8191_BYTES_MSB: 087C
STAT_RX_PACKET_8192_9215_BYTES_LSB: 0880
STAT_RX_PACKET_8192_9215_BYTES_MSB: 0884
STAT_RX_PACKET_LARGE_LSB: 0888
STAT_RX_PACKET_LARGE_MSB: 088C
STAT_RX_PACKET_SMALL_LSB: 0890
STAT_RX_PACKET_SMALL_MSB: 0894
STAT_RX_UNDERSIZE_LSB: 0898
STAT_RX_UNDERSIZE_MSB: 089C
STAT_RX_FRAGMENT_LSB: 08A0
STAT_RX_FRAGMENT_MSB: 08A4
STAT_RX_OVERSIZE_LSB: 08A8
STAT_RX_OVERSIZE_MSB: 08AC
STAT_RX_TOOLONG_LSB: 08B0
STAT_RX_TOOLONG_MSB: 08B4
STAT_RX_JABBER_LSB: 08B8
STAT_RX_JABBER_MSB: 08BC
STAT_RX_BAD_FCS_LSB: 08C0
STAT_RX_BAD_FCS_MSB: 08C4
STAT_RX_PACKET_BAD_FCS_LSB: 08C8
STAT_RX_PACKET_BAD_FCS_MSB: 08CC
STAT_RX_STOMPED_FCS_LSB: 08D0
STAT_RX_STOMPED_FCS_MSB: 08D4
STAT_RX_UNICAST_LSB: 08D8
STAT_RX_UNICAST_MSB: 08DC
STAT_RX_MULTICAST_LSB: 08E0
STAT_RX_MULTICAST_MSB: 08E4
STAT_RX_BROADCAST_LSB: 08E8
STAT_RX_BROADCAST_MSB: 08EC
STAT_RX_VLAN_LSB: 08F0
STAT_RX_VLAN_MSB: 08F4
STAT_RX_PAUSE_LSB: 08F8
STAT_RX_PAUSE_MSB: 08FC
STAT_RX_USER_PAUSE_LSB: 0900
STAT_RX_USER_PAUSE_MSB: 0904
STAT_RX_INRANGEERR_LSB: 0908
STAT_RX_INRANGEERR_MSB: 090C
STAT_RX_TRUNCATED_LSB: 0910
STAT_RX_TRUNCATED_MSB: 0914
STAT_RX_TEST_PATTERN_MISMATCH_LSB: 0918
STAT_RX_TEST_PATTERN_MISMATCH_MSB: 091C
Designing with the Subsystem
General Design Guidelines
Use the Example Design as a Starting Point
Know the Degree of Difficulty
Keep it Registered
Recognize Timing Critical Signals
Make Only Allowed Modifications
Clocking and Resets
Support for IEEE Standard 1588v2
Overview
Frame-by-Frame Timestamping Operation
Ingress
Port Descriptions
Pause Processing
TX Pause Generation
RX Pause Termination
Determining Pause Packets
User Interface
Design Flow Steps
Customizing and Generating the Subsystem
Customizing and Generating the Subsystem
Configuration Tab
MAC Options Tab
GT Selection and Configuration Tab
Shared Logic Tab
Output Generation
User Parameters
Constraining the Subsystem
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Simulation Speed Up
VCS
ModelSim
Questa Advanced Simulator
Vivado Simulator
Xcelium Parallel Simulator
Riviera-PRO Simulator
Synthesis and Implementation
Example Design
Overview
Example Design Hierarchy (GT in Example Design)
User Interface
Shared Logic Implementation
AXI4-Lite Interface Implementation
AXI4 Interface User Logic
User State Machine
Valid Write Transactions
Invalid Write Transactions
Valid Read Transactions
Invalid Read Transactions
Test Bench
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Upgrading
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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