AXI4-Lite Ports - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)

Document ID

PG251

Release Date

2023-12-12

Version

1.2 English

Table 1. AXI4-Lite Ports
Name	Direction	Clock Domain	Description
s_axi_aclk	Input		AXI4-Lite Clock
s_axi_aresetn	Input		Asynchronous active-Low Reset
s_axi_awaddr[31:0]	Input	s_axi_aclk	Write Address Bus
s_axi_awvalid	Input	s_axi_aclk	Write Address Valid
s_axi_awready	Output	s_axi_aclk	Write address acknowledge
s_axi_wdata[31:0]	Input	s_axi_aclk	Write Data Bus
s_axi_wstrb[3:0]	Input	s_axi_aclk	Strobe signal for the data bus byte lane
s_axi_wvalid	Input	s_axi_aclk	Write data valid
s_axi_wready	Output	s_axi_aclk	Write data acknowledge
s_axi_bresp[1:0]	Output	s_axi_aclk	Write transaction response
s_axi_bvalid	Output	s_axi_aclk	Write response valid
s_axi_bready	Input	s_axi_aclk	Write response acknowledge
s_axi_araddr[31:0]	Input	s_axi_aclk	Read address bus
s_axi_arvalid	Input	s_axi_aclk	Read address valid
s_axi_arready	Output	s_axi_aclk	Read address acknowledge
s_axi_rdata[31:0]	Output	s_axi_aclk	Read data output
s_axi_rresp[1:0]	Output	s_axi_aclk	Read data response
s_axi_rvalid	Output	s_axi_aclk	Read data/response valid
s_axi_rready	Input	s_axi_aclk	Read data acknowledge
pm_tick	Input	s_axi_aclk	Top level signal to read statistics counters; requires MODE_REG[30] (i.e. tick_reg_mode_sel) to be set to 0.

Additional information for the operation of the AXI4 bus is found in the AMD AXI Memory-Mapped Protocol version 1.8.

As noted previously, the top-level signal pm_tick can be used to read statistics counters instead of the configuration register TICK_REG. In this case, configuration register MODE_REG bit 30 should be set to 0. If set to 1, tick_reg is used to read the statistics counters.