AXI4-Stream Clocks and Resets - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)
Document ID
PG251
Release Date
2023-12-12
Version
1.2 English

The following table shows the clocks and reset signals of the AXI4-Stream interface.

Table 1. AXI4-Stream Interface - Clock/Reset Signals
Name Direction Clock Domain Description
tx_clk_out Output   Transmit clock for the AXI4-Stream interface. All signals between the USXGMII core and the user-side logic are synchronized to the positive edge of this signal. The AXI4-Stream clock is 312.5 MHz.
rx_clk_out Output   Receive clock for the AXI4-Stream interface. All signals between the USXGMII IP core and the user-side logic are synchronized to the positive edge of this signal. The AXI4-Stream clock is 312.5 MHz. When the RX FIFO is included, this clock will cease to exist and the RX path will be synchronized to tx_clk_out.
tx_reset Input Async Reset for the TX circuits. This signal is active-High (1=reset) and must be held High until clk is stable. The core handles synchronizing the tx_reset input to the appropriate clock domains within the core.
rx_reset   Async Reset for the RX circuits. This signal is active-High (1=reset) and must be held High until clk is stable. The core handles synchronizing the rx_reset input to the appropriate clock domains within the core.
The following table shows the AXI4-Stream transmit interface signals.
Table 2. Transmit AXI4-Stream Interface
Name Direction Clock Domain Description
tx_axis_tready Output tx_clk_out AXI4-Stream acknowledge signal to indicate to start the data transfer
tx_axis_tvalid Input tx_clk_out AXI4-Stream Data Valid input
tx_axis_tdata[31:0] Input tx_clk_out AXI4-Stream data (32-bit interface)
tx_axis_tlast Input tx_clk_out AXI4-Stream signal indicating End of Ethernet packet.
tx_axis_tkeep [3:0] Input tx_clk_out AXI4-Stream Data Control (4-bit interface)
tx_axis_tuser Input tx_clk_out

AXI4-Stream User sideband interface. Equivalent to the tx_errin signal.

1 indicates a bad packet has been transmitted.

0 indicates a good packet has been transmitted.
tx_unfout Output tx_clk_out TX Underflow. When this signal is High, it indicates that there has not been a sufficient data transfer and the Ethernet interface will underflow. This must not be allowed to occur. You must ensure that you transfer data whenever tx_axis_tready is High until you reach the end of the Ethernet frame.