AXI4-Stream Control and Status Ports

AXI4-Stream Control and Status Ports - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)

Document ID

PG251

Release Date

2023-12-12

Version

1.2 English

Table 1. AXI4-Stream Interface – TX Path Control/Status Signals
Name	Direction	Clock Domain	Description
ctl_tx_enable	Input	tx_clk_out	TX Enable. When sampled as a 1, this signal is used to enable the transmission of data. When sampled as a 0, only IDLEs are transmitted by the core. This input should not be set to 1 until the receiver it is sending data to is fully synchronized and ready to receive data. (that is, the receiver on the link partner is not sending a remote fault condition.) Otherwise, loss of data can occur. If this signal is set to 0 while a packet is being transmitted, the current packet transmission is completed and then the core stops transmitting any more packets.
ctl_tx_custom_preamble_enable	Input	tx_clk_out	When asserted, this signal enables the use of tx_preamblein as a custom preamble instead of inserting a standard preamble.
tx_preamblein[55:0]	Input	tx_clk_out	This is the custom preamble which is a separate input port rather than being in-line with the data. It should be valid during the start of the packet.
ctl_tx_fcs_ins_enable	Input	tx_clk_out	Enable FCS insertion by the TX core. If set to 0, the core does not add FCS to the packet. If set to 1, the core calculates and adds FCS to the packet. This input cannot be dynamically changed between packets.
ctl_tx_send_lfi	Input	tx_clk_out	Transmit Local Fault Indication (LFI) code word. Takes precedence over Remote Fault Indication (RFI).
ctl_tx_send_rfi	Input	tx_clk_out	Transmit Remote Fault Indication (RFI) code word. If sampled as a 1, the TX path transmits only RFI code words. This input should be set to 1 until the RX path is fully synchronized and is ready to accept data from the link partner.
ctl_tx_send_idle	Input	tx_clk_out	Transmit IDLE code words. If sampled as a 1, the TX path only transmits IDLE code words. This input should be set to 1 when the partner is sending RFI code words.
ctl_tx_send_umii_lfi	Input	tx_clk_out	If set to 1, the TX MAC/PCS will send LFI code words onto the line.
ctl_tx_send_umii_rfi	Input	tx_clk_out	If UMII LFI code set to 1, the TX MAC/PCS will send UMII RFI code words onto the line.
ctl_tx_ignore_fcs	Input	tx_clk_out	Enable FCS error checking at the AXI4-Stream interface by the TX core. This input only has effect when `ctl_tx_fcs_ins_enable` is Low. If set to 0 and a packet with bad FCS is being transmitted, it is not binned as good. If set to 1, a packet with bad FCS is binned as good. The error is flagged on the signals stat_tx_bad_fcs and stomped_fcs and the packet is transmitted as it was received. Statistics are reported as if there was no FCS error.
ctl_usxgmii_rate[2:0]	Input	static	User selectable USXGMII rate, valid when `ctl_umii_an_bypass` = 1; otherwise the USXGMII rate is determined through auto-negotiation. 3’b000 = 10 Mb/s 3’b001 = 100 Mb/s 3’b010 = 1 Gb/s 3’b011 = 10 Gb/s 3’b100 = 2.5 Gb/s 3’b101 = 5 Gb/s
ctl_umii_an_mr_adv_ability[15:0]	Input	tx_clk_out	This bus should be driven with the desired link advertised ability for the Auto-Negotiation function, that maps to the UsxgmiiChannelInfo message’s config field. [15] = Link Status [14:13] = 2'b00 [12] = Duplex Mode. 1 = Full Duplex, 0=Half Duplex [11:9] = Speed; for more information, refer table f N-base-T_usxgmii rev1.4 [8] = 1'b0 (EEE capability; Not supported.) [7] = 1'b0 (EEE clock stop capability; Not supported) [6:1] = 0x0 Reserved [0] = USXGMII
ctl_umii_an_mr_an_enable	Input	tx_clk_out	Refer to for Auto-Negotiation the use of these signals in the auto-negotiation operation.
ctl_umii_an_mr_restart_an	Input	tx_clk_out
ctl_umii_an_mr_main_reset	Input	tx_clk_out
ctl_umii_an_link_timer_config[3:0]	Input	tx_clk_out
ctl_umii_an_bypass	Input	tx_clk_out
stat_umii_an_mr_an_complete	Output	rx_serdes_clk	USXGMII auto-negotiation complete status signals.
stat_umii_an_mr_lp_adv_ability[15:0]	Output	rx_serdes_clk	Auto-negotiation ability advertisement from Link Partner.
stat_umii_an_mr_np_able	Output	rx_serdes_clk	Indicates next page capability. the design not supporting next page capability. it is set to 0.

Table 2. AXI4-Stream Interface – RX Path Control/Status Signals
Name	Direction	Clock Domain	Description
ctl_rx_enable	Input	rx_clk_out	RX enable. For normal operation this input must be set to 1. When set to 0, after the RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data. In this mode, there are no statistics reported and the AXI4-Stream interface is idle.
ctl_rx_custom_preamble_enable	Input	rx_clk_out	When asserted, this signal causes the side band of a packet presented on the AXI4-Stream to be the preamble as it appears on the line.
rx_preambleout[55:0]	Output	rx_clk_out	This is the preamble, and now a separate output instead of inline with data.
ctl_rx_delete_fcs	Input	rx_clk_out	Enable FCS removal by the RX core. If set to 0, the core does not remove the FCS of the incoming packet. If set to 1, the core deletes the FCS to the received packet. FCS is not deleted for packets that are less than 5 bytes. This input should only be changed while the corresponding reset input is asserted.
ctl_rx_ignore_fcs	Input	rx_clk_out	Enable FCS error checking at the AXI4-Stream interface by the RX core. If set to 0, a packet received with an FCS error is indicated as an errored frame (rx_axis_tuser=1 when rx_axis_tlast=1) If set to 1, the core does not flag an FCS error at the AXI4-Stream Interface. The statistics are reported as if the packet is good. The signal stat_rx_bad_fcs, however reports the error.
ctl_rx_max_packet_len[14:0]	Input	rx_clk_out	Any packet longer than this value is considered to be oversized. If a packet has a size greater than this value, it is truncated to this value and the `rx_axis_tuser` signal is asserted along with the `rx_axis_tlast` signal. ctl_rx_max_packet_len[14] is reserved and must be set to 0.
ctl_rx_min_packet_len[7:0]	Input	rx_clk_out	Any packet shorter than this value is considered to be undersized. If a packet has a size shorter than this value, the rx_axis_tuser signal is asserted along with the rx_axis_tlast signal.
ctl_rx_check_sfd	Input	rx_clk_out	When asserted, this input causes the MAC to check the Start of Frame Delimiter (SFD) of the received frame.
ctl_rx_check_preamble	Input	rx_clk_out	When asserted, this input causes the MAC to check the preamble of the received frame. When rx custom preamble is enabled, both ctl_rx_check_sfd, crl_rx_check_preamble are required to be disabled.
ctl_rx_force_resync	Input	rx_clk_out	RX force resynchronization input. This signal is used to force the RX path to reset and resynchronize. A value of 1 forces the reset operation. A value of 0 allows normal operation. This should normally be Low and should only be pulsed. (1 cycle minimum pulse)
stat_rx_local_fault	Output	rx_clk_out	This output is High when `stat_rx_internal_local_fault` or `stat_rx_received_local_fault` is asserted. This output is level sensitive.
stat_rx_umii_local_fault	Output	rx_clk_out	USXGMII received UMII local fault
stat_rx_remote_fault	Output	rx_clk_out	Remote fault indication status. If this bit is sampled as 1, indicates a remote fault condition was detected. If this bit is sampled as 0, remote fault condition does not exist. This output is level sensitive.
stat_rx_umii_remote_fault	Output	rx_clk_out	USXGMII has received UMII Remote fault.
stat_rx_internal_local_fault	Output	rx_clk_out	High when an internal local fault is generated due to any of the following: test pattern generation or high bit error rate (BER). Remains High as long as the fault condition persists.
stat_rx_received_local_fault	Output	rx_clk_out	High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine. Remains High as long as the fault condition persists.
stat_rx_block_lock	Output	rx_clk_out	Block lock status. A value of 1 indicates that block lock is achieved as defined in Clause 49.2.14 and management data input/output (MDIO) register 3.32.0. This output is level sensitive.
stat_rx_framing_err_valid	Output	rx_clk_out	Valid indicator for `stat_rx_framing_err`. When sampled as a 1, the value on `stat_rx_framing_err` is valid.
stat_rx_framing_err[2:0]	Output	rx_clk_out	The RX sync header bits framing error is a bus that indicates how many sync header errors were received. The value of the bus is only valid when the `stat_rx_framing_err_valid` is a 1. The values can be updated at any time and are intended to be used as increment values for sync header error counters.
stat_rx_hi_ber	Output	rx_clk_out	High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by IEEE Std. 802.3. Corresponds to management data input/output (MDIO) register bit 3.32.1as defined in Clause 49.2.14. This output is level sensitive.