CONFIGURATION_USXGMII_AN: 00C8 - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)
Document ID
PG251
Release Date
2023-12-12
Version
1.2 English
Table 1. CONFIGURATION_USXGMII_AN: 00C8
Bits Default Type Signal
0 0 RW ctl_umii_an_bypass
4:1 000 RW ctl_umii_an_link_timer_config
5 0 RW ctl_umii_an_mr_an_enable
6 0 RW ctl_umii_an_mr_main_reset
7 0 RW ctl_umii_an_mr_restart_an
10:8 011 RW

ctl_usxgmii_rate

  • 000: 10 Mb/s
  • 001: 100 Mb/s
  • 010: 1 Gb/s
  • 011: 10 Gb/s
  • 100: 2.5 Gb/s
  • 101: 5 Gb/s
15:11 0 RO Reserved for future use
16 1 RW USXGMII
22:17 0 RW Reserved for future use
23 0 RW EEE clock stop capability; Not supported
24 0 RW EEE capability; Not supported.
27:25 011 RW Speed; refer to table f N-base-T_usxgmii rev1.4
28 1 RW Duplex Mode. 1 = Full Duplex, 0=Half Duplex
29 0 RW Reserved for future use
30 0 RO AN acknowledge
31 0 RW Link Status