The 32-bit USXGMII IP core MAC is configured to operate its RX side on a single RX recovered clock (async gearbox option on the GTH or GTY transceiver for a bubble-less data path running with a 312.5 MHz clock).
Clocking and Reset
The entire TX side and the AXI4-Stream
interface run on a single 312.5 MHz clock. This clock is provided to user logic on the
tx_clk_out port.
All signals between the USXGMII IP core and the user-side
RX logic are synchronized to the positive edge of the rx_clk_out clock,
which is set to a frequency of 312.5 MHz. When the RX FIFO is included,
rx_clk_out will not be present and the RX path will be synchronized to
tx_clk_out.
The IP core has a simple reset structure. The single
tx_reset input is asserted High to reset the TX data path. This reset can
be deasserted when the clk clock is stable.
The RX GT interface logic is reset by asserting the
rx_serdes_reset signal. The rx_reset signal resets the
internal RX data path. When the clk clock is stable, the
rx_reset can be released. Following that when the
rx_serdes_clk is stable the rx_serdes_reset can be
released.