Configuration Tab - 1.2 English

USXGMII Ethernet Subsystem Product Guide (PG251)
Document ID
PG251
Release Date
2023-12-12
Version
1.2 English

The Configuration tab provides the basic core configuration options. Default values are pre-populated in all tabs.

Figure 1. Configuration Tab (AMD Versal™ Adaptive SoC)

The following screenshot details the Configuration Tab for on AMD UltraScale™ / AMD UltraScale+™ .

Figure 2. Configuration Tab (AMD UltraScale™ /UltraScale+)

Table 1. Configuration Options
Option Values Default
General
Select Core USXGMII MAC+PCS/PMA 32-bit USXGMII MAC+PCS/PMA 32-bit
Data Path Interface AXI4-Stream 1 AXI4-Stream
Num of Cores 6

1

2

3

4

 1
Clocking Asynchronous 2 Asynchronous
PCS/PMA Options
Auto Negotiation Logic Checked 3 Checked
Control and Statistics Interface
Control and Statistics interface

Control and Status Vectors

Include AXI4-Lite

Control and Status Vectors
Include Statistics Counters Checked and Unchecked 4 Checked
Statistics Resource Type 5 Registers, block RAM Registers
  1. The AXI4-Stream interface is visible and is the only available option.
  2. Asynchronous clocking is the only option available. In this mode TXOUTCLK sources the TXUSRCLK and RXOUTCLK sources the RXUSRCLK.
  3. The USXGMII standard mandates that the auto negotiation logic is always enabled. AMD Versal™ devices do not support Auto-Negotiation feature. You can assert the core input signal, ctl_umii_an_bypass, to by-pass auto negotiation logic and run the core at a fixed data-rate.
  4. The Statistics Counters are available in the register map only when you enable the Include Statistics Counters option. Otherwise, the Statistics Counters are not available.
  5. Statistics Resource Type block RAM option inclusion is planned for future release.
  6. The Number of Cores will be 1 only for the Versal devices and multi-core support will not be supported as GT will always be in the example design/outside the core.