This section contains information about constraining the subsystem.
Required Constraints
The USXGMII IP core is delivered with the AMD XDC constraints file.
Device, Package, and Speed Grade Selections
The USXGMII IP core is available for allAMD UltraScale™ , AMD UltraScale+™ and AMD Versal™ adaptive SoC devices and transceivers.
Clock Frequencies
The USXGMII IP core has two clocks. Both clocks are 312.5
MHz. The clk provides a clock to the TX and RX AXI4-Stream
datapath. This clock must be the user interface clock generated by the GT TXUSRCLK output.
The rx_serdes_clk is generated by the GTs RX interface as the RXUSRCLK
output.
Clock Management
Not Applicable
Clock Placement
Not Applicable
Banking
Not Applicable
Transceiver Placement
Not Applicable
I/O Standard and Placement
Not Applicable