The GT Selection and Configuration tab enables you to configure the serial transceiver features of the core.
Figure 1. GT Selection and Configuration Tab (Versal Adaptive SoC)
Figure 2. GT Selection and
Configuration Tab (UltraScale/UltraScale+)
| Option | Values | Default |
|---|---|---|
| GT Location | ||
|
Select whether the GT IP is included in the core or in the example design |
Include GT subcore in core Include GT subcore in example design |
Include GT subcore in core |
| GT Clocks | ||
| GT RefClk (In MHz) |
103.125 128.90625 156.25 161.1328125 206.25 257.8125 309.375 312.5 322.265625 |
161.1328125 |
| GT DRP Clock (In MHz) | 10 – 156.25 MHz | 100 |
| Core to GT Association | ||
| GT Type |
GTY GTH |
GTY |
| GT Selection |
Options based on device/ package Quad groups. For example: Quad X0Y1 Quad X0Y2 Quad X0Y3 ... |
Quad X0Y1 |
| Lane-00 to Lane-03 |
Auto filled based on device/ package. For example, if Num of Core = 4, and GT Selection = Quad X0Y1, four lanes are: X0Y4 X0Y5 X0Y6 X0Y7 |
Checked |
| Others | ||
| Enable Pipeline Registers | Checked, Unchecked | Unchecked |
|
Enable Additional GT Control/ Status and DRP Ports |
Checked, Unchecked | Unchecked |