Use the Example Design as a Starting Point
Each release is delivered as a complete reference design that includes a sample test bench for simulation. Transceivers are included, targeted to the particular AMD device requested for that release. In most cases, you need to re-assign the transceivers according to the device pinout specific to your board layout. You might also wish to generate new custom transceivers using the AMD Vivado™ Design Suite with characteristics suited to your board.
Know the Degree of Difficulty
USXGMII IP Core designs are challenging to implement in any technology, and the degree of difficulty is further influenced by:
- Maximum system clock frequency
- Targeted device architecture
- Nature of your application
All USXGMII core implementations need careful attention to system performance requirements. Pipelining, logic mapping, placement constraints, and logic duplication are all methods that help boost system performance.
Keep it Registered
To simplify timing and increase system performance in an FPGA design, keep all inputs and outputs registered between your application and the core. This means that all inputs and outputs from your application should come from, or connect to a flip-flop. While registering signals cannot be possible for all paths, it simplifies timing analysis and makes it easier for the Vivado Design Suite to place and route the design.
Recognize Timing Critical Signals
The timing constraints file that is provided with the example design for the core identifies the critical signals and the timing constraints that should be applied.
Make Only Allowed Modifications
The USXGMII IP Core is not user-modifiable. Do not make any modifications because these modifications can have adverse effects on system timing and protocol functionality. You can submit supported user configurations of the USXGMII core to AMD Technical Support for implementation.
You are encouraged to modify the transceivers included with the example design. Use the latest GT Wizard which is part of the Vivado Design Suite. Some features that might need to be customized are the transceiver placement, reference clocks, and optional ports, among others.